参数资料
型号: KMPC8347VVAJF
厂商: Freescale Semiconductor
文件页数: 22/99页
文件大小: 0K
描述: IC MPU PWRQUICC II 672-TBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 672-LBGA
供应商设备封装: 672-TBGA(35x35)
包装: 托盘
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
29
Ethernet: Three-Speed Ethernet, MII Management
8.2.3.1
TBI Transmit AC Timing Specifications
Table 29 provides the TBI transmit AC timing specifications.
Figure 14 shows the TBI transmit AC timing diagram.
Figure 14. TBI Transmit AC Timing Diagram
8.2.3.2
TBI Receive AC Timing Specifications
Table 30 provides the TBI receive AC timing specifications.
Table 29. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
GTX_CLK clock period
tTTX
—8.0
ns
GTX_CLK duty cycle
tTTXH/tTTX
40
60
%
GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay
tTTKHDX
1.0
5.0
ns
GTX_CLK clock rise (20%–80%)
tTTXR
——
1.0
ns
GTX_CLK clock fall time (80%–20%)
tTTXF
——
1.0
ns
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit
timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V)
or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until
the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on
three letters representing the clock of a particular function. For example, the subscript of tTTX represents the TBI (T) transmit
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Table 30. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
PMA_RX_CLK clock period
tTRX
16.0
ns
PMA_RX_CLK skew
tSKTRX
7.5
8.5
ns
RX_CLK duty cycle
tTRXH/tTRX
40
60
%
GTX_CLK
TXD[7:0]
tTTX
tTTXH
tTTXR
tTTXF
tTTKHDX
TX_EN
TX_ER
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