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| 型号： | KMPC8349ZUAJF |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 43/87页 |
| 文件大小： | 0K |
| 描述： | IC MPU PWRQUICC II 672-TBGA |
| 标准包装： | 2 |
| 系列： | MPC83xx |
| 处理器类型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 533MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 672-LBGA |
| 供应商设备封装： | 672-TBGA（35x35） |
| 包装： | 托盘 |
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
48
Freescale Semiconductor
PCI
Table 46 provides the PCI AC timing specifications at 33 MHz.
PORESET to REQ64 hold time
tPCRHRX
050
ns
6
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.
2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The setup and hold time is with respect to the rising edge of PORESET.
Table 46. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—11
ns
2
Output hold from clock
tPCKHOX
2—
ns
2
Clock to output high impedance
tPCKHOZ
—14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from clock
tPCIXKH
0
—
ns
2, 4
REQ64 to PORESET setup time
tPCRVRH
5
—
clocks
5
PORESET to REQ64 hold time
tPCRHRX
050
ns
5
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going
to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went
high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. The setup and hold time is with respect to the rising edge of PORESET.
Table 45. PCI AC Timing Specifications at 66 MHz1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
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| KMPC8358CVRAGDGA | 功能描述:微处理器 - MPU 8358 PBGA NON-ENC NO-PB RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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