参数资料
| 型号： | KS8001S |
| 厂商： | Micrel Inc |
| 文件页数： | 4/44页 |
| 文件大小： | 0K |
| 描述： | TXRX 10/100 LINKMD 3.3V 48-SSOP |
| 标准包装： | 30 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | IEEE 802 |
| 电源电压： | 1.8 V ~ 3.3 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 管件 |
| 配用： | KS8001L-EVAL-ND - EVAL KIT EXPERIMENTAL KS8001L |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
KS8001
Micrel
May 2005 – SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
KS8001
MICREL CONFIDENTIAL. DO NOT DISTRIBUTE.
12
Functional Description
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, NRZ to NRZI conversion, MLT-3 encoding and
transmission. The circuitry starts with a parallel-to-serial conversion, which converts the 25 MHz, 4-bit nibbles into a 125 MHz serial
bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from
NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.65 K
resistor for
the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX driver.
100BASE-TX Receive
The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock
recovery, NRZI to NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equalization filter to
compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a
function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. In this design, the variable
equalizer will make an initial estimation based upon comparisons of incoming signal strength against some known cable
characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against environmental changes
such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effects of base line wander and to improve the dynamic range. The differential data conversion circuit converts
the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to
convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized
25 MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the
positive edge. When no valid data is present, the clock recovery circuit is locked to the 25 M
Ηz reference clock and both TXC and
RXC clocks continue to run.
PLL Clock Synthesizer
The KS8001 generates 125 M
Ηz, 25 MΗz and 20 MΗz clocks for system timing. An internal crystal oscillator circuit provides the
reference clock for the synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8001 will continue to encode and
transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the
boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into
the 100BASE- driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into
outputs with a typical 2.5 V amplitude. The harmonic contents are at least 27 dB below the fundamental when driven by an all-ones
Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL
performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch
circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent noises at the RX+ or RX- input from
falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KS8001
decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The
receive clock is maintained active during idle periods in between data reception.
相关PDF资料 |
PDF描述 |
|---|---|
| NB7L216MN | IC RECEIVER/DRIVER DIFF 16-QFN |
| M83723/75W10028 | CONN PLUG 2POS STRAIGHT W/SCKT |
| VI-B41-IV-B1 | CONVERTER MOD DC/DC 12V 150W |
| VI-J7Z-EY-F3 | CONVERTER MOD DC/DC 2V 20W |
| D38999/24WJ43PA | CONN RCPT 43POS JAM NUT W/PINS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KS8001S TR | 功能描述:TXRX 10/100 LINKMD 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,140 系列:AU 类型:收发器 驱动器/接收器数:1/1 规程:CAN 电源电压:5.3 V ~ 27 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:管件 其它名称:935267940512AU5790D14AU5790D14-ND |
| KS8001SI | 功能描述:TXRX 10/100 LINKMD 3.3V 48-SSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,140 系列:AU 类型:收发器 驱动器/接收器数:1/1 规程:CAN 电源电压:5.3 V ~ 27 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:管件 其它名称:935267940512AU5790D14AU5790D14-ND |
| KS800A500-1800V Y40KSEA | 制造商:LIUJING 制造商全称:LIUJING 功能描述:可控硅、晶闸管 |
| KS800A500-1800V Y40KSE | 制造商:LIUJING 制造商全称:LIUJING 功能描述:可控硅、晶闸管 |
| KS8081 | 功能描述:IC SWITCH 10/100 3PORT 128PQFP RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
发布紧急采购，3分钟左右您将得到回复。