January 2005
17
KS8999
Micrel
Group
I/O Names
Active Status
Description(Note 1)
PRSV
H
Priority buffer reserve – reserves 6KB of buffer space for the priority traffic if enabled.
0 = No priority reserve
1 = Reserve 6KB for priority traffic
Note: This is also controlled by the EEPROM registers (register 2 bit 1). The value in
the EEPROM supercedes this pin.
CFGMODE
H
Selects between EEPROM or processor for programming interface.
0 = Processor interface
1 = EEPROM interface or not programmed on this interface (SCL / SDA not used)
X1
Clock
External crystal or clock input
X2
Clock
Used when other polarity of crystal is needed. This is unused for a normal clock input.
SCL
Clock
Clock for EEPROM
SDA
I/O
Serial data for EEPROM
RST#
L
System reset
TEST
TESTEN
H
Factory test input – tie low for normal operation
SCANEN
H
Factory test input – tie low for normal operation
MUX[1:2]
H
Factory test input – leave open for normal operation
AOUT
H
Factory test output – leave open for normal operation
DOUT
H
Factory test output – leave open for normal operation
AOUT2
H
Factory test output – leave open for normal operation
DOUT2
H
Factory test output – leave open for normal operation
BTOUT
H
Factory test output – leave open for normal operation
CTOUT
H
Factory test output – leave open for normal operation
BTOUT2
H
Factory test output – leave open for normal operation
CTOUT2
H
Factory test output – leave open for normal operation
TEST[1:2]
H
Factory test inputs – leave open for normal operation
AUTOMDIX
H
F/U = Enable Auto MDI/MDIX (normal operation)
D = Disable Auto MDI/MDIX
T[1:3] & T[5]
H
Factory test inputs – leave open (float) for normal operation
T[4]
H
F/D = normal operation (default)
U = Disable FEF
QH[2:5]
H
Factory test outputs – leave open for normal operation
QL[2:5]
H
Factory test outputs – leave open for normal operation
IO_SWM
H
Factory test input – tie high for normal operation
RLPBK
H
Factory test input – tie low for normal operation
BIST
H
Factory test input – tie low for normal operation
PWR
VDD_RX
2.0V for equalizer
GND_RX
Ground for equalizer
VDD_TX
2.0V for transmit circuitry
GND_TX
Ground for transmit circuitry
VDD_RCV
2.0V for clock recovery circuitry
GND_RCV
Ground for clock recovery
VDD_PLLTX
2.0V for phase locked loop circuitry
Note 1.
All unmanaged programming takes place at reset time only. For unmanaged programming: F = Float, D = Pull-down, U = Pull-up.
See
“Reference Circuits” section.