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| 型号： | KSZ8001S TR |
| 厂商： | Micrel Inc |
| 文件页数： | 4/46页 |
| 文件大小： | 0K |
| 描述： | TXRX 10/100 LINKMD 3.3V 48-SSOP |
| 标准包装： | 1,000 |
| 类型： | 收发器 |
| 规程： | MII，RMII，SMII |
| 电源电压： | 1.8V, 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
| 配用： | 576-1620-ND - BOARD EVALUATION FOR KSZ8001L |
| 其它名称： | KSZ8001STR KSZ8001STR-ND |
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Micrel
KSZ8001
June 2009
Revision 1.04
12
Functional Description
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, NRZ to NRZI conversion, MLT-3 encoding and
transmission. The circuitry starts with a parallel-to-serial conversion, which converts the 25 MHz, 4-bit nibbles into a 125 MHz serial
bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from
NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.65 K
Ω resistor for
the 1:1 transformer ratio. It has typical rise/fall times of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX driver.
100BASE-TX Receive
The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock
recovery, NRZI to NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equalization filter to
compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a
function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. In this design, the variable
equalizer will make an initial estimation based upon comparisons of incoming signal strength against some known cable
characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against environmental changes
such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effects of base line wander and to improve the dynamic range. The differential data conversion circuit converts
the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then used to
convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized
25 MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at the
positive edge. When no valid data is present, the clock recovery circuit is locked to the 25 M
Ηz reference clock and both TXC and
RXC clocks continue to run.
PLL Clock Synthesizer
The KSZ8001 generates 125 M
Ηz, 25 MΗz and 20 MΗz clocks for system timing. An internal crystal oscillator circuit provides the
reference clock for the synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KSZ8001 will continue to encode and
transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs at the
boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated into
the 100BASE- driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into
outputs with a typical 2.5 V amplitude. The harmonic contents are at least 27 dB below the fundamental when driven by an all-ones
Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL
performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch
circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent noises at the RX+ or RX- input from
falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8001
decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD) available. The
receive clock is maintained active during idle periods in between data reception.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ801S | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:1.8C, 3.3V 10/100BASE-T/TX/FX Physical Layer Transceiver |
| KSZ8021RNL | 功能描述:TXRX PHY 100BASE TX 3.3V 24QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,140 系列:AU 类型:收发器 驱动器/接收器数:1/1 规程:CAN 电源电压:5.3 V ~ 27 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:管件 其它名称:935267940512AU5790D14AU5790D14-ND |
| KSZ8021RNL TR | 功能描述:以太网 IC 3.3V, 100Base-FX Physical Layer Transceiver with RMII support (24-QFN) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8021RNL-EVAL | 功能描述:以太网开发工具 3.3V, 100Base-FX Physical Layer Transceiver w/ RMII Support - Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8021RNL-TR | 功能描述:1/1 Transceiver Full RMII 24-QFN (4x4) 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:过期 类型:收发器 协议:RMII 驱动器/接收器数:1/1 双工:全 接收器滞后:- 数据速率:- 电压 - 电源:1.8V，2.5V，3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商器件封装:24-QFN（4x4） 标准包装:1 |
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