参数资料
型号: KSZ8051MNL-EVAL
厂商: Micrel Inc
文件页数: 18/59页
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8051MNL
标准包装: 1
主要目的: 接口,以太网 PHY
嵌入式:
已用 IC / 零件: KSZ8051MNL
已供物品:
相关产品: 576-3845-ND - TXRX PHY 10/T100 3.3V 32QFN
576-3777-6-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3777-1-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3777-2-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
576-3732-ND - TXRX PHY 10/T100 3.3V MII 32-QFN
其它名称: 576-3865
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
25
M9999-070910-1.0
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for
transmission by the PHY.
TXD[1:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[1:0] while TXEN is de-asserted
are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the
frame through the final recovered dibit, and it is negated prior to the first REF_CLK that follows the final dibit. The data on
RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,
RXD[1:0] transfers two bits of recovered data from the PHY.
RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other than “00” on RXD[1:0] while CRS_DV is de-
asserted are ignored by the MAC.
Receive Error (RXER)
RXER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
Collision Detection
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
RMII Signal Diagram
The KSZ8051RNL RMII pin connections to the MAC are shown in the following figures for 25MHz Clock Mode and 50MHz
Clock Mode.
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