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参数资料
| 型号： | KSZ8051MNL-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 5/59页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8051MNL |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网 PHY |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8051MNL |
| 已供物品： | 板 |
| 相关产品： | 576-3845-ND - TXRX PHY 10/T100 3.3V 32QFN 576-3777-6-ND - TXRX PHY 10/T100 3.3V MII 32-QFN 576-3777-1-ND - TXRX PHY 10/T100 3.3V MII 32-QFN 576-3777-2-ND - TXRX PHY 10/T100 3.3V MII 32-QFN 576-3732-ND - TXRX PHY 10/T100 3.3V MII 32-QFN |
| 其它名称： | 576-3865 |
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Micrel, Inc.
KSZ8051MNL/RNL
July 2010
13
M9999-070910-1.0
Strapping Options – KSZ8051MNL
Pin Number
Pin Name
Type
(1)
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipu/O
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
The default PHY Address is 00001.
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0]
Mode
000
MII (default)
110
MII Back-to-Back
001 – 101, 111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree#
Ipu/Opu
NAND Tree Mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset,
and consequently cause the PHY strap-in pins on the MII signals to be latched to the unintended high/low states. In this case, external pull-ups (4.7K) or
pull-downs (1.0K) should be added on these PHY strap-in pins to ensure the intended values are strapped-in correctly.
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相关代理商/技术参数 |
参数描述 |
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| KSZ8051MNLI | 功能描述:TXRX PHY 10/T100 3.3V 32QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1,140 系列:AU 类型:收发器 驱动器/接收器数:1/1 规程:CAN 电源电压:5.3 V ~ 27 V 安装类型:表面贴装 封装/外壳:14-SOIC（0.154"，3.90mm 宽） 供应商设备封装:14-SO 包装:管件 其它名称:935267940512AU5790D14AU5790D14-ND |
| KSZ8051MNLI TR | 功能描述:以太网 IC 3.3V, 10Base-T/100Base-TX Physical Layer Transceiver with MII support (32-QFN, Industrial Grade) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8051MNLITR | 制造商:Micrel 功能描述:Ethernet TXRX PHY 10 T100 3.3V 32 QFN |
| KSZ8051MNLI-TR | 功能描述:1/1 Transceiver Full MII 32-QFN (5x5) 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:过期 类型:收发器 协议:MII 驱动器/接收器数:1/1 双工:全 接收器滞后:- 数据速率:- 电压 - 电源:1.8V，2.5V，3.3V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商器件封装:32-QFN（5x5） 标准包装:1 |
| KSZ8051MNL-TR | 功能描述:1/1 Transceiver Full MII 32-QFN (5x5) 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:过期 类型:收发器 协议:MII 驱动器/接收器数:1/1 双工:全 接收器滞后:- 数据速率:- 电压 - 电源:1.8V，2.5V，3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商器件封装:32-QFN（5x5） 标准包装:1 |
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