参数资料
型号: KSZ8842-16MQL-EVAL
厂商: Micrel Inc
文件页数: 29/141页
文件大小: 0K
描述: BOARD EVALUATION KSZ8842-16MQL
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-16MQL
主要属性: 2 个端口,100BASE-TX/10BASE-T,管理型
次要属性: 8/16 位接口,LinkMD 线缆诊断
已供物品: 板,CD,文档,电源
产品目录页面: 1114 (CN2011-ZH PDF)
相关产品: 576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MQLA6-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1479-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1478-5-ND - IC SWITCH 10/100 16BIT 128PQFP
其它名称: 576-1634
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
124
M9999-102207-1.9
Timing Specifications
Asynchronous Timing without using Address Strobe (ADSN = 0)
Figure 17. Asynchronous Cycle – ADSN = 0
Symbol
Parameter
Min
Typ
Max
Unit
t1
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
0
ns
A1-A15, AEN, BExN[3:0] hold after RDN inactive
(assume ADSN tied Low)
0
ns
t2
A1-A15, AEN, BExN[3:0] hold after WRN inactive
(assume ADSN tied Low)
1
t3
Read data valid to ARDY rising
0.8
ns
t4
Read data to hold RDN inactive
4
ns
t5
Write data setup to WRN inactive
4
ns
t6
Write data hold after WRN inactive
2
ns
t7
Read active to ARDY Low
8
ns
t8
Write inactive to ARDY Low
8
ns
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
0
40
ns
t9
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
0
80
ns
t10
ARDY low (wait time) in write cycle (Note1)
(It is 0ns to write bank select register)
(It is 36ns to write QMU data register)
0
50
ns
Note 1: When CPU finished current Read or Write operation, it can do next Read or Write operation even
the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the
RDN/WRN low until the ARDY returns to high.
Note 2: In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only
supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
Table 24. Asynchronous Cycle (ADSN = 0) Timing Parameters
t6
t5
t1
t4
t3
t2
valid
Addr, AEN, BExN
ADSN
Read Data
RDN, WRN
Write Data
t7
ARDY
(Read Cycle)
ARDY
(Write Cycle)
t8
t9
t10
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