参数资料
型号: KSZ8842-PMBL AM
厂商: Micrel Inc
文件页数: 25/119页
文件大小: 0K
描述: IC ETHERNET SW 2PORT 100-LFBGA
标准包装: 260
控制器类型: 以太网开关控制器
接口: PCI
电源电压: 3.1 V ~ 3.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LFBGA
供应商设备封装: 100-LFBGA
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-1636-ND - BOARD EVALUATION KSZ8842-PMQL
其它名称: 576-3348
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
13
M9999-100207-1.5
Pin
Number
Pin
Name
Type
Pin Function
41
NC
No connect
42
AGND
Gnd
Analog ground
43
VDDA
P
1.2V analog VDD
44
NC
No connect
45
RXP1
I/O
Physical receive (MDI) or transmit (MDIX)signal (+ differential)
46
RXM1
I/O
Physical receive (MDI) or transmit (MDIX) signal (– differential)
47
AGND
Gnd
Analog ground
48
TXP1
I/O
Physical transmit (MDI) or receive (MDIX) signal (+ differential)
49
TXM1
I/O
Physical transmit (MDI) or receive (MDIX) signal (– differential)
50
VDDATX
P
3.3V analog VDD
51
VDDARX
P
3.3V analog VDD
52
RXM2
I/O
Port 2 physical receive (MDI) or transmit (MDIX)signal (- differential)
53
RXP2
I/O
Port 2 physical receive(MDI) or transmit (MDIX) signal (+ differential)
54
AGND
Gnd
Analog ground
55
TXM2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
56
TXP2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
57
VDDA
P
1.2 analog VDD
58
AGND
Gnd
Analog ground
59
NC
No connect
60
NC
No connect
61
ISET
O
Set physical transmit output current
Pull-down this pin with a 3.01K 1% resistor to ground.
62
AGND
Gnd
Analog ground
63
VDDAP
P
1.2V analog VDD for PLL
64
AGND
Gnd
Analog ground
65
X1
I
66
X2
O
25MHz crystal/oscillator clock connections
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is not connected.
Note: Clock is ±50ppm for both crystal and oscillator.
67
RSTN
Ipu
Hardware Reset, Active Low
RSTN will cause the KSZ8842-PMQL to reset all of its functional blocks. RSTN must be
asserted for a minimum duration of 10 ms.
68
PAR
I/O
PCI Parity
Even parity computed for PAD [31:0] and CBE [3:0]N, master drives PAR for address
and write data phase, target drives PAR for read data phase.
69
FRAMEN
I/O
PCI Cycle Frame
This signal is asserted low to indicate the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the
transaction in a bus master mode. As a target, the device monitors this signal before
decoding the address to check if the current transaction is addressed to it.
70
IRDYN
I/O
PCI Initiator Ready
As a bus master, this signal is asserted low to indicate valid data phases on PAD [31:0]
during write data phases, indicates it is ready to accept data during read data phases.
As a target, it’ll monitor this IRDYN signal that indicates the master has put the data on
the bus.
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