参数资料
型号: KSZ8851-16MLL
厂商: Micrel Inc
文件页数: 20/84页
文件大小: 0K
描述: IC CTLR MAC/PHY NON-PCI 48-LQFP
产品培训模块: KSZ8851 10/100 Embedded Controllers
标准包装: 250
控制器类型: 以太网控制器,MAC/PHY
接口: 总线
电源电压: 1.8V,2.5V,3.3V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-3292-ND - BOARD EVALUATION KSZ8851-16MLL
其它名称: 576-3252
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
27
Revision 2.2
The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 7.
Bit
Description
15-11
Reserved.
10-0
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer memory for better
utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this field. Writing a 0
value to this field is not permitted.
Table 7. Transmit Byte Count Format
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8851-16MLL does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by
the KSZ8851-16MLL. It is treated transparently as data both for transmit operations.
Frame Transmitting Path Operation in TXQ
This section describes the typical register settings for transmitting packets from host processor to KSZ8851-16MLL with
generic bus interface. User can use the default value for most of the transmit registers. The following Table 8 describes all
registers which need to be set and used for transmitting single frames.
Register Name
[bit](offset)
Description
TXCR[3:0](0x70)
TXCR[8:5](0x70)
Set transmit control function as below:
Set bit 3 to enable transmitting flow control. Set bit 2 to enable transmitting padding.
Set bit 1 to enable transmitting CRC. Set bit 0 to enable transmitting block operation.
Set transmit checksum generation for ICMP, UDP, TCP and IP packet.
TXMIR[12:0](0x78)
The amount of free transmit memory available is represented in units of byte. The TXQ memory (6 KByte)
is used for both frame payload and control word.
TXQCR[0](0x80)
For single frame to transmit, set this bit 0 = 1(manual enqueue). the KSZ8851-16MLL will enable current
TX frame prepared in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before setting up another new TX frame.
TXQCR[1](0x80)
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR register) to CPU when
TXQ memory is available based upon the total amount of TXQ space requested by CPU at TXNTFSR
(0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should wait for the bit to
be cleared before set to 1 again
RXQCR[3](0x82)
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data frame)
TXFDPR[14](0x84)
Set bit 14 to enable TXQ transmit frame data pointer register increments automatically on accesses to the
data register.
IER[14][6](0x90)
Set bit 14 to enable transmit interrupt in Interrupt Enable Register
Set bit 6 to enable transmit space available interrupt in Interrupt Enable Register.
ISR[15:0](0x92)
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
TXNTFSR[15:0](0x9E)
The host CPU is used to program the total amount of TXQ buffer space which is required for next total
transmit frames size in double-word count.
Table 8. Registers Setting for Transmit Function Block
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