参数资料
| 型号： | KSZ8995M |
| 厂商： | Micrel Inc |
| 文件页数： | 29/73页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH 10/100 5PORT 128PQFP |
| 标准包装： | 66 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-PQFP（14x20） |
| 包装： | 托盘 |
| 产品目录页面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1607-ND - BOARD EVAL EXPERIMENT KSZ8995MA |
| 其它名称： | 576-1038 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页
December 2003
35
M9999-120403
KS8995M
Micrel
I2C Master Serial Bus Configuration
If a 2-wire EEPROM exists, the KS8995M can perform more advanced features like “broadcast storm protection,” “rate control,”
etc. The EEPROM should have the entire valid configuration data from register 0 to register 109 defined in the
“Memory Map,”
except the status registers. After reset, the KS8995M will start to read all 110 registers sequentially from the EEPROM. The
configuration access time (t
prgm) is less than 15ms as shown in Figure 7.
....
RST_N
SCL
SDA
t prgm <15 ms
Figure 7. KS8995M EEPROM
Configuration Timing Diagram
To configure the KS8995M with a pre-configured EEPROM use the following steps:
1. At the board level, connect pin 110 on the KS8995M to the SCL pin on the EEPROM. Connect pin 111 on the
KS8995M to the SDA pin on the EEPROM.
2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00”. This puts the KS8995M serial bus configuration
into I2C master mode.
3. Be sure the board level reset signal is connected to the KS8995M reset signal on pin 115 (RST_N).
4. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note that
the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all other data
will be ignored.
5. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KS8995M. After the reset is deasserted, the KS8995M will begin reading configuration data from the EEPROM. The
configuration access time (t
prgm) is less than 15ms.
Note: For proper operation, make sure pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KS8995M can also act as an SPI slave device. Through the SPI, the entire feature set can be enabled, including “VLAN,”
“IGMP snooping,” “MIB counters,” etc. The external master device can access any register from register 0 to register 127
randomly. The system should configure all the desired settings before enabling the switch in the KS8995M. To enable the
switch, write a one to register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To speed
configuration time, the KS8995M also supports multiple reads or writes. After a byte is written to or read from the KS8995M,
the internal address counter automatically increments if the SPI Slave Select signal (SPIS_N) continues to be driven low. If
SPIS_N is kept low after the first byte is read, the next byte at the next address will be shifted out on SPIQ. If SPIS_N is kept
low after the first byte is written, bits on the Master Out Slave Input (SPID) line will be written to the next address. Asserting
SPIS_N high terminates a read or write operation. This means that the SPIS_N signal must be asserted high and then low again
before issuing another command and address. The address counter wraps back to zero once it reaches the highest address.
Therefore the entire register set can be written to or read from by issuing a single command and address.
The KS8995M is able to support a 5MHz SPI bus. A high performance SPI master is recommended to prevent internal counter
overflow.
相关PDF资料 |
PDF描述 |
|---|---|
| RSM40DTAT | CONN EDGECARD 80POS R/A .156 SLD |
| LFEC6E-3QN208C | IC FPGA 6.1KLUTS 147I/O 208-PQFP |
| LFEC6E-3Q208C | IC FPGA 6.1KLUTS 147I/O 208-PQFP |
| RMM40DTAT | CONN EDGECARD 80POS R/A .156 SLD |
| LFXP3E-5Q208C | IC FPGA 3.1KLUTS 136I/O 208-PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8995MA | 功能描述:以太网 IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8995MA4 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| KSZ8995MAB3 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| KSZ8995MA-EVAL | 功能描述:以太网开发工具 KSZ8995MA Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8995MAI | 功能描述:以太网 IC 5 Port 10/100 Switch with PHY and Frame Buffers (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。