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参数资料
| 型号： | KSZ9021RLI |
| 厂商： | Micrel Inc |
| 文件页数： | 4/58页 |
| 文件大小： | 0K |
| 描述： | TXRX ETHERNET GB RGMII 64-LQFP |
| 标准包装： | 160 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 8/8 |
| 规程： | 千兆位以太网 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP 裸露焊盘 |
| 供应商设备封装： | 64-E-LQFP |
| 包装： | 托盘 |
| 其它名称： | 576-3636 KSZ9021RLI-ND |
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Micrel, Inc.
KSZ9021RL/RN
February 13, 2014
12
Revision 1.2
Pin Number
Pin Name
Type
(1)
Pin Function
36
RXD3 /
MODE3
I/O
RGMII Mode:
RGMII RD3 (Receive Data 3) Output /
Config Mode:
The pull-up/pull-down value is latched as MODE3 during
power-up/reset. See “Strapping Options” section for details.
37
DVDDH
P
3.3V/2.5V digital VDD
38
RXD2 /
MODE2
I/O
RGMII Mode:
RGMII RD2 (Receive Data 2) Output /
Config Mode:
The pull-up/pull-down value is latched as MODE2 during
power-up/reset. See “Strapping Options” section for details.
39
VSS
Gnd
Digital ground
40
DVDDL
P
1.2V digital VDD
41
RXD1 /
MODE1
I/O
RGMII Mode:
RGMII RD1 (Receive Data 1) Output /
Config Mode:
The pull-up/pull-down value is latched as MODE1 during
power-up/reset. See “Strapping Options” section for details.
42
RXD0 /
MODE0
I/O
RGMII Mode:
RGMII RD0 (Receive Data 0) Output /
Config Mode:
The pull-up/pull-down value is latched as MODE0 during
power-up/reset. See “Strapping Options” section for details.
43
RX_DV /
CLK125_EN
I/O
RGMII Mode:
RGMII RX_CTL (Receive Control) Output /
Config Mode:
Latched as CLK125_NDO Output Enable during power-up/reset.
See “Strapping Options” section for details.
44
DVDDH
P
3.3V/2.5V digital VDD
45
RX_ER
O
RGMII Mode:
This pin is not used and should be left as a no connect.
46
RX_CLK /
PHYAD2
I/O
RGMII Mode:
RGMII RXC (Receive Reference Clock) Output /
Config Mode:
The pull-up/pull-down value is latched as PHYAD[2] during
power-up/reset. See “Strapping Options” section for details.
47
CRS
O
RGMII Mode:
This pin is not used and should be left as a no connect.
48
MDC
Ipu
Management Data Clock Input
This pin is the input reference clock for MDIO (pin 49).
49
MDIO
Ipu/O
Management Data Input/Output
This pin is synchronous to MDC (pin 48) and requires an external pull-up resistor
to 3.3V/2.5V digital VDD in a range from 1.0k to 4.7k.
50
COL
O
RGMII Mode:
This pin is not used and should be left as a no connect.
51
INT_N
O
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up
resistor to 3.3V/2.5V digital VDD in a range from 1.0k to 4.7k when active low.
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt
output to active low (default) or active high.
52
DVDDL
P
1.2V digital VDD
53
VSS
Gnd
Digital ground
54
DVDDL
P
1.2V digital VDD
55
CLK125_NDO /
LED_MODE
I/O
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the MAC. /
Config Mode:
The pull-up/pull-down value is latched as LED_MODE during
power-up/reset. See “Strapping Options” section for details.
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