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参数资料
| 型号： | L64724BC |
| 厂商： | LSI CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 2/32页 |
| 文件大小： | 338K |
| 代理商： | L64724BC |
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10
L64724 Satellite Receiver
IBIAS
Current Bias I
Input
The IBIAS pin supplies the current bias for the I channel
ADC.
QBIAS
Current Bias Q
Input
The QBIAS pin supplies the current bias for the Q
channel ADC.
AGC/Clock Control Interface
PWRP
Power Control
Output
The PWRP signal is the positive modulated output used
for power control and can drive an external passive RC
lter that feeds the gain control stage.
Microcontroller Interface
The Microcontroller Interface connects the L64724 to a microcontroller,
such as the 64008.
A[2:0]
Address
Input
The A[2:0] signals form the receiver address bus. The
address bus is used in conjunction with an eight-bit data
bus D[7:0], a read/write strobe (READ/WRITE), a chip
select strobe (CS), and an address strobe (AS) to select,
read, and write internal registers.
AS
Address Strobe
Input
The AS signal is an active-LOW address strobe input.
The L64724 latches the address on the A[2:0] signals on
the falling edge of the AS signal.
CS
Chip Select
Input
The CS signal is an active-LOW chip select strobe input.
During a read cycle, the microcontroller must assert CS
(LOW) to access the on-chip data registers. The control-
ler must latch the data from the L64724 on the rising
edge of CS. During a write cycle, CS must be asserted
prior to data being valid from the controller to the L64724.
After the data has met the minimum setup time, the
microcontroller deasserts CS (HIGH) to strobe the data.
There is a minimum write time to allow for internal syn-
chronization. Setup and hold times are measured with
respect to the falling edge of CS.
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