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参数资料
| 型号： | L64724BC |
| 厂商： | LSI CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | PLASTIC, TQFP-80 |
| 文件页数： | 4/32页 |
| 文件大小： | 338K |
| 代理商： | L64724BC |
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12
L64724 Satellite Receiver
Control Signal Interface
The Control Signal Interface signals control the operation of the L64724.
They are not associated with any particular interface.
IDDTN
Test Pin
Input
The IDDTN pin is an LSI Logic internal test pin. Set the
IDDTN pin LOW for normal operation.
RESET
Reset
Input
RESET is an active-HIGH signal that resets all internal
data paths. RESET timing is asynchronous to the device
clocks and does not affect the conguration registers. It
performs the same operation as the reset bits specied
in the Group 4 APR 36 register.
XCTR_IN
Control Input Pin
Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the corresponding bit in the Group 3,
APR 6 register.
XCTR_OUT[3] Control Output/Sync Status Flag
Output
The XCTR_OUT[3] pin indicates the synchronization sta-
tus for one of three synchronization modules in the
L64724 (Viterbi decoder sync, DI/RS sync, and descram-
bler sync) or the XCTR.3 eld in Group 4, APR 55. For
any of the three synchronization outputs, the
XCTR_OUT[3] signal, when asserted, indicates that syn-
chronization has been achieved for the chosen sync mod-
ule. When deasserted, the signal indicates an
out-of-synchronization condition.
XCTR_OUT[2:0]
Control Output Pins
Output
The XCTR_OUT[2:0] pins are external output control
pins. They are set by programming the corresponding bits
in the Group 4, APR 55 register. XCTR_OUT[0] can
function as the Serial Clock (SCLK) signal, and
XCTR_OUT[1] can function as the Serial Data (SDATA)
signal.
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