参数资料
型号: L6564D
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, PDSO10
封装: ROHS COMPLIANT, SSOP-10
文件页数: 16/34页
文件大小: 809K
代理商: L6564D
L6564
Application information
Doc ID 16202 Rev 1
23/34
where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2fL component, will be:
shows a diagram that helps choose the time constant RFFCFF based on the
amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the
pin, the IC will not work properly if the pin is either left floating or connected directly to
ground.
Figure 36.
RFFCFF as a function of 3rd harmonic distortion introduced in the input
current
The dynamics of the voltage feedforward input, that is the output of the multiplier, is limited
downwards at 0.8 V (see Figure 35), so that cannot increase any more if the voltage on the
VFF pin is below 0.8 V. This helps to prevent excessive power flow when the line voltage is
lower than the minimum specified value.
6.4
THD optimizer circuit
The L6564 is provided with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (total harmonic distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high-
frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This will result in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
shows the internal block diagram of the THD optimizer circuit.
FF
L
3
C
R
f
2
100
%
D
π
=
D %
3
0.1110
0.01
0.1
1
10
f = 50 Hz
L
f = 60 Hz
L
R C
[s]
FF
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