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参数资料
| 型号： | L6605D |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封装： | SO-20 |
| 文件页数： | 5/10页 |
| 文件大小： | 2337K |
| 代理商： | L6605D |
±2.5%; while during line/load variation (IPP = 1mA
to 50mA; VPPI = max. 33V) the VPP range is
±5%.
An internal circuitry checks the IPP level; the pro-
tection block activates an IRQ with the proper fail-
ure code when the output current is in 51mA to
150mA range. Under the power ON/OFF thresh-
old value the logic section and the power supply
regulators are disabled.
LOGIC SECTION
L6605 includes a logic circuitry in order to protect,
both card and itself. If a failure occours an asyn-
chronous IRQ is sent to the
P; consequently the
P forces low CS signal as I/O request. After CS
variation the
P sends also one "data direction
bit" into DATA DIRECTION REGISTER.
Direction bit = "0"
Pin DATA is configurated in output and the
P
reads the 2 bit STATUS REGISTER content
Code
1st bit
2nd bit
0
No insertion
No Failure
1
Card Inserted
Failure
Failure could be overtemperature over the 2 regu-
lators (VPP, VCS).
Direction bit = "1"
Pin DATA is configurated in input to allow the 3
bit DAC loading and than the programming of
VPPo output level voltage. (see Table 1).
During card insertion only rising edge of switch
signal is detected , while during card extraction
switch level is detected.
In card extraction mode if occours a mechanical
switch bouncing, which causes a pulse on
SWITCH input pin with duration t
≥ 50s the
L6605 will have the 1st Status Register content
equal to "0" and 1 ms tshadow timing like during
card insertion mode.
Bouncing on SWITCH pin with duration T<50
s
will be transparent in the Status Register.
Figure 1: Card Insertion
L6605
4/10
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