参数资料
型号: L6728D
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: 30 A SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDSO10
封装: 3 X 3 MM, ROHS COMPLIANT, DFN-10
文件页数: 8/33页
文件大小: 1215K
代理商: L6728D
Application details
L6728D
16/33
Doc ID 16498 Rev 1
10
Application details
10.1
Compensation network
The control loop shown in Figure 5 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, the offset resistor between the FB node
and GND can be neglected in control loop calculation).
The error amplifier output is compared to the oscillator sawtooth waveform to provide the
PWM signal to the driver section. The PWM signal is then transferred to the switching node
with VIN amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT
resonance and a zero at FESR depending on the output capacitor ESR. The DC gain of the
modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage
ΔV
OSC.
Figure 5.
PWM control loop
The compensation network closes the loop, joining the VOUT and EA output with transfer
function ideally equal to -Z
F/ZFB.
The compensation goal is to close the control loop while assuring high DC regulation
accuracy, good dynamic performance and stability. To achieve this, the overall loop needs
high DC gain, high bandwidth and good phase margin.
High DC gain is achieved by giving an integrator shape to the compensation network
transfer function. The loop bandwidth (F0dB) can be fixed by choosing the correct RF/RFB
ratio. However, for stability, it should not exceed FSW/2π. To achieve a good phase margin,
the control loop gain must cross the 0 dB axis with -20 dB/decade slope.
As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.
L
R
C
OUT
ESR
R
F
C
F
C
P
R
FB
C
S
OSC
V
IN
ΔV
OSC
+
_
V
OUT
V
REF
ZF
Z
FB
PWM
COMPARATOR
ERROR
AMPLIFIER
R
S
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