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参数资料
| 型号： | L9942XPTR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 运动控制电子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, 2.5 A, PDSO24 |
| 封装： | LEAD FREE, POWER, SSO-24 |
| 文件页数： | 14/40页 |
| 文件大小： | 664K |
| 代理商： | L9942XPTR |
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L9942
Functional Description of the Logic with SPI
4
Functional Description of the Logic with SPI
4.1
Motor Stepping Clock Input( STEP)
Rising edge of signal STEP is latched. It is synchronised by internal clock. At next start of a
new PWM cycle the new values of output current limit are used to drive motor in next
position. Before start new motor step this signal has to be low for at least two internal clock
periods to reset latch.
4.2
PWM Output (PWM)
This output reflects the current duty cycle of the internal PWM controller of bridge A. High
level indicates on state to increase current through load and low level is in off state so load
current decreases depending on chosen decay mode.
4.3
Serial Peripheral Interface (SPI)
This device uses a standard 16 bit SPI to communicate with a microcontroller. The SPI can
be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0
and CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect an
internal Error Flag of the device which is a logical-or of all status bits in the Status Register
(reg7) and in the Current Profile Register 4 (reg6). The microcontroller can poll the status of
the device without the need of a full SPI-communication cycle.
4.4
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal will activate the output driver
and a serial communication can be started. The state when CSN is going low until the rising
edge of CSN will be called a communication frame.
4.5
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and latched into an internal 16 bit shift register.
The first 3 bit are interpreted as address of the data register. At the rising edge of the CSN
signal the contents of the shift register will be transferred to the selected data register. The
writing to the register is only enabled if exactly 16 bits are transmitted within one
communication frame (i.e. CSN low). If more or less clock pulses are counted within one
frame the complete frame will be ignored. This safety function is implemented to avoid an
activation of the output stages by a wrong communication frame.
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相关代理商/技术参数 |
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