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参数资料
| 型号： | L9A0212 |
| 厂商： | LSI CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 32-BIT, 85 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | PLASTIC, MO-151, BGA-256 |
| 文件页数： | 12/32页 |
| 文件大小： | 128K |
| 代理商： | L9A0212 |
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12
TinyRISC LR4102 Microprocessor
FBus registers (Cont.)
FACFG2
0x1FFF.0408
Configuration for address range 2
FACFG3
0x1FFF.040C
Configuration for address range 3
FACFG4
0x1FFF.0410
Configuration for address range 4
FACFG5
0x1FFF.0414
Configuration for address range 5
FBUSTA
0x1FFF.0418
Bus turnaround register for address range 0–5
FACMP0
0x1FFF.0440
Address compare register address range 0
FACMP1
0x1FFF.0444
Address compare register address range 1
FACMP2
0x1FFF.0448
Address compare register address range 2
FACMP3
0x1FFF.044C
Address compare register address range 3
FACMP4
0x1FFF.0450
Address compare register address range 4
FACMP5
0x1FFF.0454
Address compare register address range 5
FBUSCMP
0x1FFF.0470
Address compare register for FBus address range.
FBUSAC
0x1FFF.0474
Address compare register for FBus I/O, memory, and
configuration address range.
FBUSCFG
0x1FFF.0480
Configuration for FBus when accessing outside
programmable address range 0–5.
FSDRAM
0x1FFF.0490
Configuration for external EDO (S)DRAM
FDRAMT
0x1FFF.0494
Timing parameters for external EDO DRAM
FSDRAMT
0x1FFF.0498
Timing parameters for external SDRAM
FGPCFG
0x1FFF.04C0
Configuration for General-Purpose I/O
FGPOUTPUT
0x1FFF.04C4
Output value for General-Purpose Outputs
FGPINPUT
0x1FFF.04C8
Input value for General-Purpose Inputs
Reserved registers
Reserved
0x1FFF.0500–.06FF
Reserved for LSI Logic use
On Chip Memory (OCM), 1 Kbytes
OCM area
0x1FFF.8000–.83FF
On chip memory. Placed on CBus, 1 cycle access
Table 4
LR4102 Register Memory Map (Cont.)
Register Name
Physical Address
Description
(Sheet 2 of 2)
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