参数资料
型号: L9A0212
厂商: LSI CORP
元件分类: 微控制器/微处理器
英文描述: Microprocessor
中文描述: 32-BIT, 85 MHz, RISC PROCESSOR, PBGA256
封装: PLASTIC, MO-151, BGA-256
文件页数: 18/32页
文件大小: 128K
代理商: L9A0212
18
TinyRISC LR4102 Microprocessor
Figure 5
Input Timing with Respect to PBCLKP
Figure 6
Output Timing with Respect to PBCLKP
Figure 7
Input Timing with Respect to SDCLKP
Setup
Input
PBCLKP
Hold
Note:
PBCLKP equals the system clock (PCLKP) when the DIV C value in the Clock
module is 0b01. DIV C = 0b01 is used to show timing for signals related to the system
clock. The setting of DIV C only affects PBCLKP and the timing for signals related to
the FAPI clock (PBCLKP).
Min Output
Output
PBCLKP
Max Output
Setup
Input
SDCLKP
Hold
相关PDF资料
PDF描述
LAA110 Dual Pole OptoMOS Relays
LAA110P Dual Pole OptoMOS Relays
LAA110PTR Dual Pole OptoMOS Relays
LAA110S Dual Pole OptoMOS Relays
LAA110STR Dual Pole OptoMOS Relays
相关代理商/技术参数
参数描述
L9D112G80BG4 制造商:LOGIC 制造商全称:LOGIC 功能描述:1.2 Gb, DDR - SDRAM Integrated Module
L9D112G80BG4E10 制造商:LOGIC 制造商全称:LOGIC 功能描述:1.2 Gb, DDR - SDRAM Integrated Module
L9D112G80BG4E6 制造商:LOGIC 制造商全称:LOGIC 功能描述:1.2 Gb, DDR - SDRAM Integrated Module
L9D112G80BG4E75 制造商:LOGIC 制造商全称:LOGIC 功能描述:1.2 Gb, DDR - SDRAM Integrated Module
L9D112G80BG4E8 制造商:LOGIC 制造商全称:LOGIC 功能描述:1.2 Gb, DDR - SDRAM Integrated Module