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| 型号： | LA4032V-75TN44E |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 40/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 32MACROCELLS 44TQFP |
| 标准包装： | 160 |
| 系列： | LA-ispMACH |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 宏单元数： | 32 |
| 输入/输出数： | 30 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-TQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
7
Block CLK3
PT Clock
PT Clock Inverted
Shared PT Clock
Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
PT Initialization/CE
PT Initialization/CE Inverted
Shared PT Clock
Logic High
Initialization Control
The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set
and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB.
At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for
set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be
exchanged, providing exibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All ip-ops power up to a
known state for predictable system initialization. If a macrocell is congured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is congured to RESET on a
signal from the block-level initialization or is not congured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset
delay time has elapsed.
GLB Clock Generator
Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used
as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four
clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of com-
binations of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
CLK1
CLK2
CLK3
Block CLK0
Block CLK1
Block CLK2
Block CLK3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LA4032V-75TN48E | 功能描述:CPLD - 复杂可编程逻辑器件 Auto Grade (AEC-Q100 ) ispMACH4032V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LA4032ZC-75TN100E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZC-75TN128E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZC-75TN144E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4032ZC-75TN44E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
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