参数资料
| 型号： | LA4425PV-MPB-H |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/8页 |
| 文件大小： | 0K |
| 描述： | IC AUDIO POWER AMP 5W 44SSOP |
| 标准包装： | 30 |
| 类型： | AB 类 |
| 输出类型： | 1-通道（单声道） |
| 在某负载时最大输出功率 x 通道数量： | 6W x 1 @ 4 欧姆 |
| 电源电压： | 5 V ~ 16 V |
| 特点： | 消除爆音，过压保护，短路保护，热保护 |
| 安装类型： | * |
| 供应商设备封装： | * |
| 封装/外壳： | * |
| 包装： | * |
8
INDUSTRIAL TEMPERATURERANGE
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
TABLE 5 — CONTROL REGISTER (CR) BITS
Reset Value:
0000H.
BIT
NAME
DESCRIPTION
15
SRS
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
(SoftwareReset)
14
OEI
When 1, the TX8-15/OEI0-7 pins will be OEI0-7 and reflect the active or high-impedance state of their corresponding output
(OutputEnableIndication)
data streams. When 0, this feature is disabled and these pins are used as output data streams TX8-15.
13
OEPOL
When1,aoneonanOutputEnableIndicationpindenotesanactivestateontheoutputdatastream;zeroonanOutputEnableIndication
(Output Enable Polarity)
pin denoteshigh-impedancestate.When0,aoneonanOutputEnableIndicationpindenoteshigh-impedanceandazerodenotes
and active state.
12
AOE
When 1, TX0-15 will behave as OEI0-15 accordingly. These outputs will reflect the active or high-impedance state of the
(All Output Enable)
corresponding output data streams (TX0-15) in another IDT72V73250 if programmed identically. When 0, the TSI operates in the
normal switch mode.
11-10
Unused
Must be zero for normal operation.
9
MBP
When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits, bit
(Memory Block Program)
14 to bit 15. When 0, this feature is disabled.
8-7
BPD1-0
These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature
(Block Programming
is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to
Data)
1, the contents of the bits Block Programming Data1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of
the Connection Memory are set to 0.
6
BPE
A zero to one transition of this bit enables the memory block programming function. The Block Programming Enable and
(Begin Block
BlockProgrammingData1-0bitsintheControlRegister havetobedefinedinthesamewriteoperation.OncetheBlockProgramming
ProgrammingEnable)
Enable bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has
finished, the Block Programming Enable, Memory Block Program and Block Programming Data 1-0 bits will be reset to
zero by the device to indicate the operation is complete.
5
OSB
When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When
(Output Stand By)
either ODE = 1 or Output Stand By =1, the output serial streams drivers function normally.
4
SFE
A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame
(Start Frame Evaluation)
Alignment Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this
bit to zero for at least one frame.
3-0
Unused
Must be zero for normal operation.
15
14
13
12
11
10
9876543210
SRS
OEI
OEPOL
AOE
0
MBP
BPD1
BPD0
BPE
OSB
SFE
0000
TABLE 6 — CONNECTION MEMORY BITS
15
14
13
12
11
10
9876543210
MOD1
MOD0
0
SAB3
SAB2
SAB1
SAB0
CAB8
CAB7
CAB6
CAB5
CAB4
CAB3
CAB2
CAB1
CAB0
Bit
Name
Description
15, 14
MOD1-0
MOD1
MOD0
MODE
(Switching Mode Selection)
0
Variable Delay mode
0
1
Constant Delay mode
1
0
Processor mode
1
OutputHigh-impedance
13
Unused
Must be zero for normal operation.
12-9
SAB3-0
The binary value is the number of the data stream for the source of the connection.
(Source Stream Address Bits)
8-0
CAB8-0
The binary value is the number of the channel for the source of the connection.
(Source Channel Address Bits)
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