参数资料
型号: LAMXO640C-3TN144E
厂商: Lattice Semiconductor Corporation
文件页数: 12/77页
文件大小: 0K
描述: IC FPGA AUTO 640LUTS 144TQFP
标准包装: 60
系列: LA-MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 4.9ns
电压电源 - 内部: 1.71 V ~ 3.465 V
宏单元数: 320
输入/输出数: 113
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
其它名称: 220-1640
LAMXO640C-3TN144E-ND
April 2006
Data Sheet DS1003
2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1003 Introduction_01.0
Features
■ Non-volatile, Innitely Recongurable
Instant-on – powers up in microseconds
Single chip, no external conguration memory
required
Excellent design security, no bit stream to
intercept
Recongure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
■ AEC-Q100 Tested and Qualied
■ Sleep Mode
Allows up to 100x static current reduction
■ TransFR Reconguration (TFR)
In-eld logic update while system operates
■ High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
■ Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM Embedded Block
RAM
Up to 7.5 Kbits distributed RAM
Dedicated FIFO control logic
■ Flexible I/O Buffer
Programmable sysIO buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
■ sysCLOCK PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
■ System Level Support
IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming
Introduction
The LA-MachXO automotive device family is optimized
to meet the requirements of applications traditionally
addressed by CPLDs and low capacity FPGAs: glue
logic, bus bridging, bus interfacing, power-up control,
and control logic. These devices bring together the best
features of CPLD and FPGA devices on a single chip in
AEC-Q100 tested and qualied versions.
The devices use look-up tables (LUTs) and embedded
block memories traditionally associated with FPGAs for
exible and efcient logic implementation. Through non-
volatile technology, the devices provide the single-chip,
Table 1-1. LA-MachXO Automotive Family Selection Guide
Device
LAMXO256E/C
LAMXO640E/C
LAMXO1200E
LAMXO2280E
LUTs
256
640
1200
2280
Dist. RAM (Kbits)
2.0
6.0
6.25
7.5
EBR SRAM (Kbits)
0
9.2
27.6
Number of EBR SRAM Blocks (9 Kbits)
0013
VCC Voltage
1.2/1.8/2.5/3.3V
1.2
Number of PLLs
0012
Max. I/O
78
159
211
271
Packages
100-pin Lead-Free TQFP (14x14 mm)
78
74
73
144-pin Lead-Free TQFP (20x20 mm)
113
256-ball Lead-Free ftBGA (17x17 mm)
159
211
324-ball Lead-Free ftBGA (19x19 mm)
271
LA-MachXO Automotive Family Data Sheet
Introduction
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LAMXO640E 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet
LAMXO640E-3FTN256E 功能描述:CPLD - 复杂可编程逻辑器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LAMXO640E-3TN100E 功能描述:CPLD - 复杂可编程逻辑器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LAMXO640E-3TN144E 功能描述:CPLD - 复杂可编程逻辑器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LAMXO640LUTSC-3FTN256E 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet