参数资料
型号: LC4128ZC-75TN100E
厂商: Lattice Semiconductor Corporation
文件页数: 4/99页
文件大小: 0K
描述: IC CPLD 128MACROCELLS 100TQFP
标准包装: 90
系列: ispMACH® 4000Z
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 1.7 V ~ 1.9 V
逻辑元件/逻辑块数目: 8
宏单元数: 128
输入/输出数: 64
工作温度: -40°C ~ 130°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
Figure 2. Generic Logic Block
To GRP
Clock
Generator
1+OE
1+OE
1+OE
1+OE
36 Inputs
1+OE
from GRP
1+OE
1+OE
1+OE
To
Product Term
Output Enable
Sharing
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
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LC4128ZC-75TN100I 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC4128ZE5MN100C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs
LC4128ZE5MN100CES 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs
LC4128ZE5MN100I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs
LC4128ZE5MN100IES 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:1.8V In-System Programmable Ultra Low Power PLDs