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| 型号： | LC51024VG-75F676I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 7.5 ns, PBGA676 |
| 封装： | FBGA-676 |
| 文件页数： | 1/48页 |
| 文件大小： | 237K |
| 代理商： | LC51024VG-75F676I |
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5kvg_09
ispMACH 5000VG Family
3.3V In-System Programmable
SuperBIG, SuperWIDE High Density PLDs
December 2001
Data Sheet
TM
Features
■ High Density
768 to 1,024 macrocells
196 to 384 I/Os
■ sysCLOCK PLL – Timing Control
Multiply and divide factors between 1 and 32
Clock shifting capability ± 3.5ns in 500ps steps
Multiple output frequencies
External feedback capability for board-level
clock deskew
LVDS/LVPECL clock input capability
■ High Speed Logic Implementation
SuperWIDE 68-input logic block
Up to 160 product terms per output
Hierarchical routing structure provides fast inter-
connect
■ sysIO Capability
LVCMOS 1.8, 2.5 and 3.3
LVTTL
SSTL 2 (I & II)
SSTL 3 (I & II)
CTT 3.3, CTT 2.5
HSTL (I & III)
PCI-X, PCI 3.3
GTL+
AGP-1X
5V tolerance
Programmable drive strength
■ Ease of Design
Product term sharing
Extensive clocking and OE capability
■ Easy System Integration
3.3V power supply
Hot socketing
Input pull-up, pull-down or bus-keeper
Open drain capability
Slew rate control
Macrocell-based power management
IEEE 1149.1 boundary scan testable
In-system programmable via IEEE 1532 ISC
compliant interface
ispMACH 5000VG Introduction
The ispMACH 5000VG represents the third generation
of Lattice’s SuperWIDE CPLD architecture. Through
their wide 68-input blocks, these devices give signi-
cantly improved speed performance for typical designs
over architectures with fewer inputs.
The ispMACH 5000VG takes the unique benets of the
SuperWIDE architecture and extends it to higher densi-
ties referred to as SuperBIG, by using the combination
of an innovative product term architecture and a two-
tiered hierarchical routing architecture. Additionally,
sysCLOCK and sysIO capabilities have been added to
maximize system-level performance and integration.
Table 1. ispMACH 5000VG Family Selection Guide
ispMACH
5768VG
ispMACH
51024VG
Macrocells
768
1,024
User I/O Options
196/304
304/384
tPD (ns)
5.0
tS – Set-up with 0 Hold (ns)
3.0
tCO (ns)
4.4
fMAX (MHz)
178
Supply Voltage (V)
3.3V
Package
256-ball fpBGA
484-ball fpBGA
676-ball fpBGA
相关PDF资料 |
PDF描述 |
|---|---|
| LC5768VG-5F484C | |
| LC51024VG-12F484I | |
| LC5768VG-5F256C | |
| LC51024VG-75F484C | |
| LC51024VG-10F484I | |
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