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| 型号： | LC5384B-5Q208C |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 6.5 ns, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 12/66页 |
| 文件大小： | 240K |
| 代理商： | LC5384B-5Q208C |
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Lattice Semiconductor
ispMACH 5000B Family Data Sheet
2
Figure 1. Functional Block Diagram
The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form groups of ve
product term clusters, which feed the product term sharing array and the macrocell directly. The ispMACH 5000B allows
up to 35 product terms to be connected to a single macrocell via the Product Term Sharing Array. The macrocell is
designed to provide exible clocking and control functionality with the capability to select between global, product
term, and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if
required, the sysIO cell.
All I/Os in the ispMACH 5000B family are sysIO capable, which are split into four banks. Each bank has a separate
I/O power supply and reference voltage. The sysIO cells allow operation with a wide range of today's emerging
interface standards. Within a bank, inputs can be set to a variety of standards providing the reference voltage
requirements of the chosen standards are compatible. Within each bank, the outputs can be set to differing stan-
dards providing the I/O power supply requirements of the chosen standard are compatible. Support for this wide
range of standards allows designers to achieve signicantly higher board-level performance compared to the more
traditional LVCMOS standards. Table 1 shows the key attributes and packages for the ispMACH5000B devices.
ispMACH 5000B Architecture
The ispMACH 5000B Family of In-System Programmable (ISP) high density programmable logic devices is
based on Generic Logic Blocks (GLBs) and a global routing pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the GRP. Enhanced switching resources are provided to allow signals in the GRP to
drive any or all of the GLBs. This mechanism allows fast, efcient connections across the entire device. Figure 1
shows the basic ispMACH 5000B architecture.
Generic Logic Block
Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms
and three GLB-level control product terms. The GLB has 68 inputs from the GRP, which are available in both true
I/O Bank 0
Global
Routing
Pool
I/O Bank 3
I/O Bank 1
I/O Bank 2
GCLK0
GCLK1
TOE
VCCO0
TDO
TMS
TCK
TDI
VREF0
VCCO1
VREF1
GCLK3
GCLK2
VCCO3
VREF3
VCCO2
VREF2
RESETB
GOE1
GOE2
Generic
Logic
Block
Generic
Logic
Block
Generic
Logic
Block
Generic
Logic
Block
Discontinued
Product
(PCN
#02-06).
Contact
Rochester
Electronics
for
Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
相关PDF资料 |
PDF描述 |
|---|---|
| LC5512B-10F256I | |
| LC5512B-75Q208I | |
| LC5128B-10T128I | |
| LC5384B-5F256C | |
| LC5512B-75F256I | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC5384B-5Q208I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5384B-75F256C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5384B-75F256I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5384B-75Q208C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5384B-75Q208I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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