Lattice Semiconductor
ispMACH 5000B Family Data Sheet
19
ispMACH 5128B Internal Timing Parameters
1
Over Recommended Operating Conditions
Parameter
Description
-3
-5
-75
-10
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
In/Out Delays
tIN
Input Buffer Delay
-
0.30
-
0.60
-
2.00
-
2.40
ns
tGCLK_IN
Global Clock Input Buffer Delay
-
1.00
-
1.50
-
1.40
-
1.90
ns
tGOE
Global OE Pin Delay
-
1.60
-
2.60
-
3.00
-
4.40
ns
tBUF
Delay through Output Buffer
-
0.50
-
0.80
-
1.80
-
2.50
ns
tEN
Output Enable Time
-
0.90
-
1.10
-
2.50
-
3.10
ns
tDIS
Output Disable Time
-
0.90
-
1.10
-
2.50
-
3.10
ns
tRST
Global Rest Pin Delay
-
1.20
-
2.20
-
2.70
-
3.60
ns
Routing Delays
tROUTE
Delay through GRP
-
1.60
-
2.50
-
2.60
-
3.70
ns
tPTSA
Product Term Sharing Array
-
1.10
-
2.10
-
2.60
-
3.40
ns
tPDb
5-PT Bypass Propogation Delay
-
0.60
-
1.10
-
1.10
-
1.40
ns
tPDi
Macrocell Propogation Delay
-
0.30
-
0.50
-
0.00
-
0.00
ns
tINREG
Input Buffer to Macrocell Register Delay
-
2.50
-
3.10
-
2.20
-
3.60
ns
tFBK
Internal Feedback Delay
-
0.00
-
0.00
-
0.00
-
0.00
ns
Register/Latch Delays
tS
D-Register Setup Time (Global Clock)
0.20
-
0.30
-
0.70
-
0.90
-
ns
tS_PT
D-Register Setup Time (Product Term Clock)
0.20
-
0.20
-
0.70
-
0.90
-
ns
tSL_PT
Latch Setup Time (Product Term Clock)
0.20
-
0.20
-
0.70
-
0.90
-
ns
tH
D-Register Hold Time
1.50
-
2.70
-
4.30
-
5.60
-
ns
tCOi
Register Clock to Output/Feedback Mux Time
-
0.70
-
0.70
0.80
1.10
ns
tCES
Clock Enable Setup Time
3.30
-
4.30
-
4.70
-
5.00
-
ns
tCEH
Clock Enable Hold Time
0.20
-
0.40
-
0.50
-
0.60
-
ns
tSL
Latch Setup Time
0.20
-
0.30
-
0.70
-
0.90
-
ns
tHL
Latch Hold Time
1.50
-
2.70
-
4.30
-
5.60
-
ns
tGOi
Latch Gate to Output/Feedback Mux Time
-
0.70
-
0.60
-
0.80
-
1.60
ns
tPDLi
Propogation Delay through Transparent Latch
to Output/Feedback Mux
-
0.50
-
0.50
-
0.50
-
0.50
ns
tSRi
Asynchronous Reset or Set to Output/Feed-
back MUX Delay
-
0.80
-
2.00
-
3.00
-
3.90
ns
tSRR
Asynchronous Reset or Set Recovery Delay
1.50
-
2.70
-
4.00
-
6.00
-
ns
Control Delays
tBCLK
GLB PT Clock Delay
-
1.70
-
2.40
-
2.80
-
3.20
ns
tPTCLK
Macrocell PT Clock Delay
-
1.50
-
2.10
-
2.40
-
2.70
ns
tBSR
Block PT Set/Reset Delay
-
1.20
-
1.70
-
1.90
-
2.10
ns
tPTSR
Macrocell PT Set/Reset Delay
-
0.80
-
1.10
-
1.20
-
1.30
ns
tGPTOE
Global PT OE Delay
-
1.40
-
2.80
-
2.90
-
2.80
ns
tPTOE
Macrocell PT OE Delay
-
1.20
-
1.80
-
1.40
-
0.80
ns
Timing v.1.0
1. Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
Discontinued
Product
(PCN
#02-06).
Contact
Rochester
Electronics
for
Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm