参数资料
型号: LC5512MC-75FN484I
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
中文描述: EE PLD, 9.5 ns, PBGA484
封装: LEAD FREE, FPBGA-484
文件页数: 32/95页
文件大小: 923K
代理商: LC5512MC-75FN484I
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
38
tPDPRWH
R/W Hold time after
Clock Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tPDPDATAS
Data Setup before
Clock Time
-0.27
-0.27
-0.22
-0.22
-0.21
ns
tPDPDATAH
Data Hold time after
Clock Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tPDPRCLKO
Read Clock to
Output Delay
5.08
5.02
5.66
5.45
8.54
ns
tPDPCLKSKEW
Opposite Clock
Cycle Delay
1.40
1.40
1.76
1.76
1.83
ns
tPDPRSTO
Reset to RAM
Output Delay
3.30
3.30
4.13
4.13
4.29
ns
tPDPRSTR
Reset Recovery
Time
1.20
1.20
1.50
1.50
1.56
ns
tPDPRSTPW
Reset Pulse Width
0.14
0.14
0.18
0.18
0.19
ns
Dual Port RAM
tDPMSAS
Memory Select A
Setup Before R/W A
Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPMSAH
Memory Select
Hold time after R/W
A Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPCEAS
Clock Enable A
Setup before Clock
A Time
3.72
3.72
3.72
3.72
4.84
ns
tDPCEAH
Clock Enable A
Hold time after
Clock A Time
-2.95
-2.95
-2.95
-2.95
-2.27
ns
tDPADDAS
Address A Setup
before Clock A Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPADDAH
Address A Hold
time after Clock A
Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPRWAS
R/W A Setup before
Clock A Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPRWAH
R/W A Hold time
after Clock A Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPDATAAS
Write Data A Setup
before Clock A Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPDATAAH
Write Data A Hold
time after Clock A
Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
tDPMSBS
Memory Select B
Setup Before R/W B
Time
-0.27
-0.27
-0.27
-0.27
-0.21
ns
tDPMSBH
Memory Select
Hold time after R/W
B Time
-0.01
-0.01
-0.01
-0.01
-0.01
ns
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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