参数资料
型号: LC5512MC-75FN484I
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
中文描述: EE PLD, 9.5 ns, PBGA484
封装: LEAD FREE, FPBGA-484
文件页数: 38/95页
文件大小: 923K
代理商: LC5512MC-75FN484I
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
43
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Units
tPWH
Input clock, high time
80% to 80%
1.2
ns
tPWL
Input clock, low time
20% to 20%
1.2
ns
tR, tF
Input Clock, rise and fall time
20% to 80%
3.0
ns
tINSTB
Input clock stability, cycle to cycle (peak)
+/- 250
ps
fMDIVIN
M Divider input, frequency range
10
320
MHz
fMDIVOUT
M Divider output, frequency range
10
320
MHz
fNDIVIN
N Divider input, frequency range
10
320
MHz
fNDIVOUT
N Divider output, frequency range
10
320
MHz
fVDIVIN
V Divider input, frequency range
100
400
MHz
fVDIVOUT
V Divider output, frequency range
10
320
MHz
tOUTDUTY
Output clock, duty cycle
40
60
%
tJIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference.
10 MHz < fMDIVOUT < 20 MHz or
100MHz < fVDIVIN < 160 MHz
1
+/- 250
ps
Clean reference.
20 MHz < fMDIVOUT < 320 MHz and
160MHz < fVDIVIN < 320 MHz
1
+/- 150
ps
TJIT(PERIOD)
2
Output clock, period jitter (peak)
Clean reference.
10 MHz < fMDIVOUT < 20 MHz or
100MHz < fVDIVIN < 160 MHz
1
+/- 300
ps
Clean reference.
20 MHz < fMDIVOUT < 320 MHz and
160MHz < fVDIVIN < 320 MHz
1
+/- 150
ps
tCLK_OUT_DLY
Input clock to CLK_OUT delay
Internal feedback
3.0
ns
tPHASE
Input clock to external feedback delta
External feedback
600
ps
tLOCK
Time to acquire phase lock after input stable
25
us
tPLL_DELAY
Delay increment (Lead/Lag)
Typical = +/- 250ps
+/- 120 +/- 550
ps
tRANGE
Total output delay range (lead/lag)
+/- 0.84 +/- 3.85
ns
tPLL_RSTW
Minimum reset pulse width
1.8
ns
tCLK_IN
3
Global clock input delay
1.0
ns
tPLL_SEC_DELAY Secondary PLL output delay (tPLL_DELAY)—
1.5
ns
1. This condition assures that the output phase jitter will remain within specification.
2. Accumulated jitter measured over 10,000 waveform samples.
3. Internal timing for reference only.
相关PDF资料
PDF描述
LC5256MC-4FN256C
LC5512MC-45FN256C
LC5768MC-5FN484C
LC5512MC-45FN484C
LC51024MB-75FN672I
相关代理商/技术参数
参数描述
LC5512MC-75FN672C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-75FN672I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-75Q208C 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC5512MC-75Q208I 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100
LC5512MC-75Q256C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family