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| 型号： | LC5512MV-75FN256I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 9/99页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 512MACROCELLS 256FPBGA |
| 标准包装： | 90 |
| 系列： | ispXPLD® 5000MV |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目： | 16 |
| 宏单元数： | 512 |
| 输入/输出数： | 193 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FPBGA（17x17） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
13
FIFO Mode
In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The
read and write clocks can be different or the same dependent on the application. Four flags show the status of the
FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are pro-
grammable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communica-
tions applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read
address.
In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 12 shows the block diagram of the FIFO.
Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share
the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead
mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared
by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various reg-
isters.
Figure 12. FIFO Block Diagram
Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode
Register
Input
Source
Write Data,
Write Enable
Clock
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
N/A
Full and
Almost Full
Flags
Clock
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
Read Data,
Empty and
Almost Empty
Flags
Clock
RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
‘
68 Inputs
From
Routing
Write Clock (WCLK)
Write Enable (WE)
Reset (RST)
Read Enable (RE)
Read Clock (RCLK)
Reset_RP (RSTRP)
Write Data
(DI[0:0-31])
16,384-bit
SRAM
Array
FIFO
Control
Logic
*Control logic can be
duplicated in adjacent MFB
in 32-bit mode
RESET
CLK0
CLK3
CLK1
CLK2
Read Data
(DO[0:0-31])
FIFO
Flags*
Full, Empty,
Almost Full,
AlmostEmpty
SELECT
DEVICES
DISCONTINUED
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| LC5512MV-75FN484C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5512MV-75FN484I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5512MV-75FN672C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-75FN672I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-75Q208C | 功能描述:CPLD - 复杂可编程逻辑器件 3.3V 149 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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