参数资料
型号: LC72122V
厂商: SANYO SEMICONDUCTOR CO LTD
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封装: SSOP-20
文件页数: 3/22页
文件大小: 346K
代理商: LC72122V
No. 6113-11/22
LC72122V
Continued from preceding page.
DO Output Data (Serial Data Output) Structure
3. OUT mode
DO Output Data
No.
Control block/data
Description
Related data
IF counter control data
IFIN pin input sensitivity control data. This data should be set to 1 in normal operation.
(11)
IFS
Setting this data to 0 switches the LC72122V to a reduced input sensitivity mode in which
the sensitivity is reduced by 10 to 30 mVrms.
Sub-charge pump control
This data controls the sub-charge pump (PDS) which is provided for fast locking.
(12)
data
By setting SUBC to 1, applications can set the sub-charge pump circuit to the operating
UL0, UL1
SUBC
state and increase the speed of frequency looking.
IC test data
IC test data
TEST 0 to TEST2
TEST0
(13)
TEST1
All three bits must be set to 0.
TEST2
All the test data is set to 0 at a power-on reset.**
(14)
DNC
Data is set to 0
No.
Control block/data
Description
Related data
I/O port data
Data latched from the states of the I/O ports, pins IO1 and IO2.
I2, I1
This data reflects the pin states, regardless of whether they are in input or output mode.
The data is latched when OUT mode is selected.
I1
← IO1 pin state
High: 1
I2
← IO2 pin state
Low: 0
PLL unlock data
Data latched from the state of the unlock detection circuit
UL
← 0: Unlocked
UL
← 1: Locked or in detection stopped mode
IF counter binary data
Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19 to C0
C19
← Binary counter MSB
C0
← Binary counter LSB
(1)
(2)
(3)
IOC1,
IOC2
UL0,
UL1
CTE,
GT0,
GT1
*
Note: * Data with a value of “0”
**Note : Although the IC is initialized after power is first applied by the power on reset circuit, applications must also send a full set of data over the CCB bus
immediately after power is first applied to assure safe and stable operation.
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