参数资料
型号: LC72122V
厂商: SANYO SEMICONDUCTOR CO LTD
元件分类: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封装: SSOP-20
文件页数: 9/22页
文件大小: 346K
代理商: LC72122V
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlock detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock
determination requires a time longer than the period of the reference frequency. However, immediately after changing
the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference
frequency.
No. 6113-17/22
LC72122V
Figure 1 Unlock Detection Timing
For example, if fref is 1 kHz (and thus the period is 1 ms), after changing the divisor N, the system must wait at least
2 ms before checking for the unlocked state.
Figure 2 Circuit Structure
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