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参数资料
| 型号： | LC72131 |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP22 |
| 封装： | SDIP-22 |
| 文件页数： | 2/23页 |
| 文件大小： | 405K |
| 代理商： | LC72131 |
2. DI Control Data Functions
No. 4921-10/23
LC72131, 72131M
No.
Control block/data
Functions
Related data
Programmable divider data Data that sets the divisor of the programmable divider.
P0 to P15
A binary value in which P15 is the MSB. The LSB changes depending on
DVS and SNS. (*: don’t care)
Note: P0 to P3 are ignored when P4 is the LSB.
DVS, SNS
Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches
the input frequency range. (*: don’t care)
Note: See the “Programmable Divider Structure” item for more information.
Reference divider data
Reference frequency (fref) selection data.
R0 to R3
Note: PLL INHIBIT
The programmable divider block and the IF counter block are stopped, the FMIN,
AMIN, and IFIN pins are set to the pull-down state (ground), and the charge pump
goes to the high impedance state.
XS
Crystal resonator selection
XS = 0: 4.5 MHz
XS = 1: 7.2 MHz
The 7.2 MHz frequency is selected after the power-on reset.
IF counter control data
IF counter measurement start data
CTE
CTE = 1: Counter start
CTE = 0: Counter reset
GT0, GT1
Determines the IF counter measurement period.
IFS
Note: See the “IF Counter Structure” item for more information.
I/O port specification data
Specifies the I/O direction for the bidirectional pins IO1 and IO2.
IOC1, IOC2
Data: 0 = input mode, 1 = output mode
Output port data
Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports
BO1 to BO4, IO1, IO2
Data: 0 = open, 1 = low
The data = 0 (open) state is selected after the power-on reset.
(1)
(2)
(3)
(4)
(5)
IOC1
IOC2
DVS
SNS
LSB
Divisor setting (N)
Actual divisor
1
*
P0
272 to 65535
Twice the value of the setting
0
1
P0
272 to 65535
The value of the setting
0
P4
4 to 4095
The value of the setting
DVS
SNS
Input pin
Input frequency range
1
*
FMIN
10 to 160 MHz
0
1
AMIN
2 to 40 MHz
0
AMIN
0.5 to 10 MHz
GT1
GT0
Measurement time (ms)
Wait time (ms)
0
4
3 to 4
0
1
8
3 to 4
1
0
32
7 to 8
1
64
7 to 8
R3
R2
R1
R0
Reference frequency (kHz)
0
100
0
1
50
0
1
0
25
0
1
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1
0
10
1
0
1
9
1
0
1
0
5
1
0
1
0
3
1
0
1
15
1
0
PLL INHIBIT + Xtal OSC STOP
1
PLL INHIBIT
Continued on next page.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC72131D | 制造商:Panasonic Industrial Company 功能描述:IC |
| LC72131K | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72131K_12 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72131KC-Z1 | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Bulk |
| LC72131KM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
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