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参数资料
| 型号： | LC72144M |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 2/22页 |
| 文件大小： | 307K |
| 代理商： | LC72144M |
Control Data Functions
No. 5377-10/22
LC72144M
No.
Control section/
Function
Related data
data
Programmable
divider data
P0 to P15,
DVS, SNS
Sub-charge
pump
control data
PDC0, PDC1
Reference
divider data
R0 to R3
(1)
(2)
(3)
UL0, UL1, DLC
Data that sets the programmable divider’s divisor. It is a binary value and P15 is the MSB. The LSB
differs depending on the DVS and SNS bits. (!: don’t care)
Note: When P4 is the LSB, P0 to P3 are ignored.
These bits select the signal input pin (FMIN or AMIN) for the programmable divider and switch the input
frequency range.
Note: See the “Programmable Divider Structure” item for details.
Data that controls the sub-change pump
Note: The sub-charge pump can form a high-speed lockup circuit when combined with the PD0 and
PD1 pins (the main charge pump).
See the item on the structure of the charge pump for details.
Data that selects the reference frequency (fref)
Note: 1. Cannot be used when the crystal oscillator frequency is 10.25 or 10.35 MHz.
Note: 2. Cannot be used when the crystal oscillator frequency is 10.25 MHz.
Note: 3. PLL inhibit (backup mode)
The programmable divider block is stopped and FMIN and AMIN are both pulled down to
ground. The charge pump output goes to the floating state.
DVS
SNS
LSB
Divisor setting (N)
1
!
P0
272 to 65535
0
1
P0
272 to 65535
0
P4
4 to 4095
DVS
SNS
Input port
Input frequency range (MHz)
1
!
FMIN
10 to 160
0
1
AMIN
2 to 40
0
AMIN
0.5 to 10
PDC1
PDC0
Sub-charge pump state
0
!
High impedance
1
0
Charge pump operates (when unlocked)
1
Charge pump operates (normal operation)
R3
R2
R1
R0
Reference frequency (kHz)
0
100*1
0
1
50
0
1
0
25
0
1
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1
0
10
1
0
1
9*2
1
0
1
0
5
1
0
1
0
3*2
1
0
1
30*2
1
0
*3, PLL inhibited and crystal oscillator stopped
1
*3, PLL inhibited
Continued on next page.
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