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参数资料
| 型号： | LC72144M |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 5/22页 |
| 文件大小： | 307K |
| 代理商： | LC72144M |
Continued from preceding page.
No. 5377-13/22
LC72144M
No.
Control section/
Function
Related data
data
Crystal
oscillator circuit
XS0, XS1, XB
Phase
comparator
control data
DZ0, DZ1
Charge pump
control data
DLC
LSI test data
TEST0, TEST1,
TEST2
(11)
(12)
(13)
(14)
R0 to R3
Data that selects the crystal oscillator element
Note: The 10.25 MHz setting is selected after the power on reset.
Data that controls the crystal oscillator element buffer output
XB = 0: Buffer output off (This mode is selected after the power on reset.)
= 1: Buffer output on
Note: Turn off the XBUF output in FM reception mode (PD0 pin used).
Data that controls the phase comparator dead band
Note: DZA is selected after power-on reset.
Data that forces the charge pump output to the low level (VSS level).
DLC = 1: Low level
= 0: Normal operation
Note: If a deadlock occurs due to the VCO oscillator being stopped by the VCO control voltage (Vtune)
becoming 0, the deadlock can be resolved by setting the charge pump output to the low level and
then setting Vtune to VCC.
This data is set to the normal operating mode state after the power on reset.
Data that controls LSI testing
This data must all be set to 0, i.e.:
TEST0 = 0
TEST1 = 0
TEST2 = 0
Note: All the test data is set to 0 after the power on reset.
XS1
XS0
Xtal OSC
0
4.5 MHz
0
1
7.2 MHz
1
0
10.25 MHz
1
10.35 MHz
DZ1
DZ0
Insensitive band (dead zone) mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
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