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参数资料
| 型号： | LC7218M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 2/16页 |
| 文件大小： | 282K |
| 代理商： | LC7218M |
Serial Data I/O Methods
The LC7218 supports a total of three I/O modes: two control data input (serial data input) modes and one DO output
(serial data output) mode. Data I/O is performed after the mode has been determined.
The mode is selected by four data items (A0 to A3) synchronized with a clock (the CL pin) applied before the CE pin is
set high. The mode is determined when the CE pin goes high.
1. In the serial data input modes (modes 1 and 2), t1 ≥ 1.5 s, t2 ≥ 0 s, t3 ≥ 1.5 s, and t4 < 1.5 s.
Mode 1: A total of 40 bits, the four mode selection bits and the 36 control data bits (from D0 to T1), are input from
the DI pin in synchronization with the clock (CL) signal.
Mode 2: A total of 28 bits, the four mode selection bits and 24 control data bits (from D0 to CTEN), are input from
the DI pin in synchronization with the clock (CL) signal.
No. 4758-10/16
LC7218, 7218M, 7218JM
Mode
A3
A2
A1
A0
Item
Function
This mode is used to input all 36 bits of the control data (serial input data).
10
001
Serial data input (all bits)
This mode is used for initialization following power on and to change data that
cannot be changed in mode 2. All 36 bits of the control data is input from the
LC7218 DI pin.
This mode is used to input a subset (24 bits) of the control data (serial input
data).
Serial data input
This mode is used to change three data items: the programmable divider data
20
010
(partial input)
(D0 to D15), the output port data (O0 to O6) and the general-purpose counter
start data (CTEN), for a total of 24 bits. The other 12 bits of control data are not
changed by a mode 2 operation. (Use mode 1 when the other 12 bits must be
changed.)
The DO output mode (serial data output) is used to output three data items from
30
011
Serial data output
the DO pin: the input port data, the general-purpose counter binary data and the
PLL unlock state data.
0 to 0
1 to 0
0 to 0
Invalid setting
This mode is invalid and does not support any data input or output operations.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC7218M-TLM-E | 制造商:Sony Semiconductor Solutions Division 功能描述: |
| LC7219 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers |
| LC72191 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191JM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191JMA-AH | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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