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参数资料
| 型号： | LC7218M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 3/16页 |
| 文件大小： | 282K |
| 代理商： | LC7218M |
2. In serial data output mode (mode 3), t1 ≥ 1.5 s, t2 ≥ 0 s, t3 ≥ 1.5 s, and t5 < 1.5 s. (However, note that since the
DO pin is an n-channel open drain output, the transition time depends on the value of the pull-up resistor.)
Mode 3: Serial output mode (mode 3) is selected by the four bits of mode selection data.
When the CE pin goes high, IO is output from the DO pin. After that, the internal shift register is shifted
and the next bit is output from the DO pin on each falling edge of the CL signal.
(Thus 27 clock cycles are required to output all data through the UL0 bit after CE goes high.)
When this mode is selected, at the point the CE pin falls to the low level, the DO pin will be forcibly set to
the high level. The DO pin will go low if the IN0 pin input changes state or if a general-purpose counter
measurement completes.
(General-purpose counter completion takes precedence over changes in the IN0 pin signal.)
Structure of the Programmable Divider
Note: 1. The actual divisor will be twice the set value when FMIN (A) is used.
For example, if the divisor setting is 1000 the actual divisor will be 2000 and if the divisor setting is 1001 the
actual divisor will be 2002. In other words, the channel skip will be twice the reference frequency.
2. To set the channel skips of 1, 5 and 9 kHz using FMIN (A), the crystal oscillator should be changed to 3.6
MHz. However, the times listed in the table that follows change since they are referenced to the crystal
oscillator frequency.
Note that care must be taken to prevent overtone oscillation when a 3.6 MHz crystal oscillator is used.
No. 4758-11/16
LC7218, 7218M, 7218JM
DV
SP
Input pin
Divisor setting
Actual divisor
Input frequency range (MHz)
(A)
1
*
FMIN
256 to 65536
Twice the set value
10 to 130
(B)
0
1
AMIN
256 to 65536
The set value
2 to 40
(C)
0
AMIN
4 to 4096
The set value
0.5 to 10
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相关代理商/技术参数 |
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|---|---|
| LC7218M-TLM-E | 制造商:Sony Semiconductor Solutions Division 功能描述: |
| LC7219 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers |
| LC72191 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191JM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| LC72191JMA-AH | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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