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| 型号： | LC82161B-E |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封装： | SQFP-208 |
| 文件页数： | 2/19页 |
| 文件大小： | 225K |
| 代理商： | LC82161B-E |
LC82161B-E
No.7775-10/19
Continued from preceding page
Power Supply System (28 pins)
DVDD3
Power supply
Digital system power supply (3.3 V)
DVDD2
Power supply
Digital system power supply (2.5 V)
DGND
Power supply
Digital system ground
AVDD3
Power supply
Analog system power supply (3.3 V)
AGND
Power supply
Analog system ground
PVDD2
Power supply
PLL power supply (2.5 V)
PGND
Power supply
PLL ground
Clocks
The clock is supplied to three blocks: the DSP block, the ARM block, and the analog block. An 8.192 MHz external
oscillator element is used.
The DSP block operating clock is variable, and can be set over the range 40 to 60 MHz with register settings. The DSP
block clock frequency can be dropped to 1/2 to 1/16 of its usual frequency according to system control block register
settings. It is also possible to fully power down the system by stopping the clock.
The ARM block consists of the ARM7 itself, peripheral circuits, and the Ethernet MAC block. The ARM block operating
clock has a frequency of 51.2 MHz. The ARM block clock frequency can be dropped to 1/2 to 1/16 of its usual frequency
according to system control block register settings. Clock supply to the individual peripheral blocks and the Ethernet MAC
block can be stopped to reduce power consumption.
The analog block consists of the A/D converter and the D/A converter. The analog block operates from a 4.096 MHz clock.
A register setting that stops this clock to reduce power consumption is provided.
PLL
XTAL
8.192 MHz
1/2
DSP block
Analog block
40 to 60 MHz
4.096 MHz
51.2 MHz
Divider
1/1 to 1/16
Divider
1/1 to 1/16
Divider
ARM block
Divider
Figure 1 Clock System Diagram
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