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参数资料
| 型号： | LC876596B |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | QIP-100 |
| 文件页数： | 3/23页 |
| 文件大小： | 682K |
| 代理商： | LC876596B |
LC876596B/80B
No.6717-11/23
2. Recommended Operating Range at Ta=-30
°C to +70°C, VSS1=VSS2=0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD[V]
min.
typ.
max.
unit
Operating
supply voltage
range
VDD(1)
VDD1=VDD2=
VDD3=VDD4
0.294
s ≤ tCYC ≤
200
s
4.5
6.0
Hold voltage
VHD
VDD1
RAM and the
register data are
kept in HOLD
mode.
2.0
6.0
Pull-down
voltage
VP
4.5–6.0
-35
VDD
VIH(1)
Port 0,3: CMOS output
option
Port 8
Output disable
4.5–6.0
0.3VDD
+0.7
VDD
VIH(2)
Port 0,3: N-ch open drain
output
Output disable
4.5–6.0
0.3VDD
+0.7
13.5
VIH(3)
Port 1
Port71,72,73
P70 port input/interrupt
Output disable
4.5–6.0
0.3VDD
+0.7
VDD
VIH(4)
S16 to S51
Output P-channel
Tr. OFF
4.5–6.0
0.3VDD
+1.0
VDD
VIH(5)
P70 Weak signal input
Output disable
4.5–6.0 0.75VDD
VDD
VIH(6)
Port 70
Watchdog timer
Output disable
4.5–6.0
0.9VDD
VDD
Input high
voltage
VIH(7)
XT1, XT2, CF1, RES
4.5–6.0 0.75VDD
VDD
VIL(1)
Port 0,3: CMOS output
option
Port 8
Output disable
4.5–6.0
VSS
0.15VDD
+0.4
VIL(2)
Port 0,3: N-ch open drain
output
Output disable
4.5–6.0
VSS
0.15VDD
+0.4
VIL(3)
Port 1
Port 71,72,73
P70 port input/interrupt
Output disable
4.5–6.0
VSS
0.1VDD
+0.4
VIL(4)
S16 to S51
Output P-channel
Tr. OFF
4.5–6.0
-35
0.2VDD
VIL(5)
Port 87 weak signal input Output disabled
4.5–6.0
VSS
0.25VDD
VIL(6)
Port 70
Watchdog timer
Output disabled
4.5–6.0
VSS
0.8VDD
-1.0
Input low
voltage
VIL(7)
XT1,XT2,CF1, RES
4.5–6.0
VSS
0.25VDD
V
Operation
cycle time
tCYC
4.5–6.0
0.294
200
s
CF2 open circuit
system clock
divider set to 1/1
external clock
DUTY = 50±50%
4.5–6.0
0.1
10
MHz
External system
clock
frequency
fEXCF(1)
CF1
CF2 open circuit
system clock
divider set to 1/2
4.5–6.0
0.2
20
Continued/
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