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参数资料
| 型号： | LC876596B |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | QIP-100 |
| 文件页数： | 7/23页 |
| 文件大小： | 682K |
| 代理商： | LC876596B |
LC876596B/80B
No.6717-15/23
4. Serial Input/Output Characteristics at Ta=-30
°C to +70°C, VSS1=VSS2=0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD[V]
min.
typ.
max.
unit
Cycle Time
tSCK(1)
4/3
tSCKL(1)
2/3
Low Level
pulse width
tSCKLA(1)
2/3
tSCKH(1)
2/3
High Level
pulse width
tSCKHA(1)
SCK0(P12)
Refer to figure 6
4.5–6.0
3
Cycle Time
tSCK(2)
2
Low Level
pulse width
tSCKL(2)
1
In
p
u
tc
loc
k
High Level
pulse width
tSCKH(2)
SCK1(P15)
Refer to figure 6
4.5–6.0
1
Cycle Time
tSCK(3)
4/3
tCYC
tSCKL(3)
1/2
Low Level
pulse width
tSCKLA(2)
3/4
tSCKH(3)
1/2
High Level
pulse width
tSCKHA(2)
SCK0(P12)
CMOS output option
Refer to figure 6
4.5–6.0
2
tSCK
Cycle Time
tSCK(4)
2
tCYC
Low Level
pulse width
tSCKL(4)
1/2
S
e
rial
clo
c
k
Out
p
ut
c
lo
ck
High Level
pulse width
tSCKH(4)
SCK1(P15)
CMOS output option
Refer to figure 6
4.5–6.0
1/2
tSCK
Data set-up time
tsDI
0.03
Se
ri
a
li
nput
Data hold time
thDI
SI0(P10),
SI1(P13),
SB0(P11),
SB1(P14)
Measured with respect
to SI0CLK leading
edge.
Refer to figure 6
4.5–6.0
0.03
Se
ri
a
lout
put
Output delay
time
tdDO
SO0(P12),
SO1(P15),
SB0(011),
SB1(P14)
Measured with respect
to SI0CLK trailing
edge.
When port is open
drain: Time delay
from SI0CLK trailing
edge to the SO data
change.
Refer to figure 6
4.5–6.0
1/3
tCYC
+0.05
s
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