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参数资料
| 型号： | LF3310QC15 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Horizontal / Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 13/21页 |
| 文件大小： | 287K |
| 代理商： | LF3310QC15 |
DEVICES INCORPORATED
Video Imaging Products
13
LF3310
Horizontal / Vertical Digital Image Filter
11/08/2001-LDS.3310-H
ADDR
1
COEF
0
COEF
1
COEFFICIENT SET 1
CLK
HLD/VLD
HCF/VCF
11-0
W1
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
HPAUSE/VPAUSE
COEF
7
ADDR
1
DATA
1
ADDR
2
CONFIGURATION REGISTER
CLK
W2
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
HPAUSE/VPAUSE
DATA
1
SELECT REGISTER
W1
HLD/VLD
HCF/VCF
11-0
F
IGURE
15. C
ONFIGURATION
AND
S
ELECT
R
EGISTER
L
OADING
S
EQUENCE
WITH
HPAUSE
AND
VPAUSE I
MPLEMENTATION
F
IGURE
14. C
OEFFICIENT
B
ANK
L
OADING
S
EQUENCE
WITH
HPAUSE
AND
VPAUSE I
MPLEMENTATION
HLD goes LOW, the Horizontal LF
Interface
TM
is enabled for data input.
The first value fed into the interface
on HCF
11-0
is an address which
determines what the interface is going
to load. The three most significant
bits (HCF
11-9
) determine if the LF
Interface
TM
will load coefficient banks
or Configuration/ Control Registers
(see Table 8). The nine least signifi-
cant bits (HCF
8-0
) are the address for
whatever is to be loaded (see
Tables 9-14). For example, to load
address 15 of the horizontal coefficient
banks, the first data value into the
LF Interface
TM
should be 00FH. To
load horizontal limit register 10, the
first data value should be C0AH. The
first address value should be loaded into
the interface on the same clock cycle that
latches the HIGH to LOW transition of
HLD (see Figures 12 and 13).
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the inter-
face will expect eight values to be
loaded into the device after the
address value. The eight values are
coefficients 0 through 7. When
loading select or Configuration
Registers, the interface will expect one
value after the address value. When
loading round registers, the interface
will expect four values after the
address value. When loading limit
registers, the interface will expect two
values after the address value.
Figures 12 and 13 show the data
loading sequences for the coefficient
banks and Configuration/ Control
Registers.
Both HPAUSE and VPAUSE allow the
user to effectively slow the rate of data
loading through the LF Interface
TM
.
When HPAUSE is HIGH, the LF
Interface
TM
affecting the data used for
the Horizontal Filter is held until
HPAUSE is returned to a LOW.
When VPAUSE is HIGH, the LF
Interface
TM
affecting the data used for
the Vertical Filter is held until
VPAUSE is returned to a LOW.
Figures 14 through 17 display the
effects of both HPAUSE and VPAUSE
while loading coefficient and control
data.
Table 15 shows an example of loading
data into the coefficient banks. The
following data values are written into
address 10 of coefficient banks 0
through 7: 210H, 543H, C76H, 9E3H,
701H, 832H, F20H, 143H. Table 16
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相关代理商/技术参数 |
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| LF3310QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3310QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3311 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3312 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:12-Mbit Frame Buffer / FIFO |
| LF3320 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal Digital Image Filter |
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