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参数资料
| 型号： | LF3310QC15 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Horizontal / Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 8/21页 |
| 文件大小： | 287K |
| 代理商： | LF3310QC15 |
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
8
Video Imaging Products
11/08/2001-LDS.3310-H
When the filter is configured for an
odd number of taps, the data which
will appear at the output of the last
I/ D Register in the forward data path
on the next clock cycle is fed into the
first I/ D Register in the reverse data
path. Bit 5 in Configuration Register
1 configures the filter for an even or
odd number of taps.
When interleaved data is fed through
the device and an even tap filter is
desired, the filter should be config-
ured for an even number of taps (Bit 5
of CR
1
set to “0”) and the I/ D Regis-
ter length should match the number
of data sets interleaved together.
When interleaved data is to be fed
through the device and an odd tap
filter is desired, the filter should be
set to Odd-Tap Interleave Mode. Bit 0
of Configuration Register 1 configures
the filter for Odd-Tap Interleave
Mode. When the filter is configured
for Odd-Tap Interleave Mode, data
from the next to last I/ D Register in
the forward data path is fed into the
first I/ D Register in the reverse data
path.
When the filter is configured for an
odd number of taps (interleaved or
non-interleaved modes), the filter is
structured such that the center data
value is aligned simultaneously at the
A and B inputs of the last ALU in the
forward data path. In order to
achieve the correct result, the user
must divide the coefficient by two.
Data Reversal
Data reversal circuitry is placed after
the multiplexer which routes data
from the forward data path to the
reverse data path (see Figure 10).
When decimating, the data stream
must be reversed in order for data to
be properly aligned at the inputs of
the ALUs. When data reversal is
enabled, the circuitry uses a pair of
LIFOs to reverse the order of the data
sent to the reverse data path. When
TXFR goes LOW, the LIFO sending
data to the reverse data path becomes
the LIFO receiving data from the
forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data
to the reverse data path. The device
must see a HIGH to LOW transition
of TXFR in order to switch LIFOs. If
decimating by N, TXFR should go low
once every N clock cycles. When data
reversal is disabled, the circuitry
functions like an I/ D Register. When
feeding interleaved data through the
filter, data reversal should be
disabled. Bit 6 of Configuration
Register 1 enables or disables data
reversal.
Horizontal Rounding
The horizontal filter output may be
rounded by adding the contents of
one of the sixteen horizontal round
registers to the horizontal filter output
F
IGURE
10.
D
ATA
R
EVERSAL
1
LIFO A
LIFO B
TXFR
F
IGURE
11. H
ORIZONTAL
AND
V
ERTICAL
R
OUND
/S
ELECT
/L
IMIT
C
IRCUITRY
R
R
32
L
L
24
4
HRSL
3-0
R
R
32
L
L
24
4
VRSL
3-0
RND
LIMIT
32
12
RND
LIMIT
32
12
12
12
VERTICAL RSL
HORIZONTAL RSL
DATA IN
32
DATA IN
32
DATA OUT
DATA OUT
S
S
5
S
S
5
SELECT
SELECT
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相关代理商/技术参数 |
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| LF3310QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3310QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3311 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3312 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:12-Mbit Frame Buffer / FIFO |
| LF3320 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal Digital Image Filter |
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