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参数资料
| 型号： | LF3330QC12 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 3/15页 |
| 文件大小： | 138K |
| 代理商： | LF3330QC12 |
DEVICES INCORPORATED
Video Imaging Products
3
LF3330
Vertical Digital Image Filter
11/08/2001–LDS.3330-M
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers
.
Inputs
DIN
11-0
— Data Input
DIN
11-0
is the 12-bit registered data
input port. Data is latched on the rising
edge of CLK.
VB
11-0
— Field Filtering Data Input
VB
11-0
is the 12-bit registered data
input port used only when implement-
ing Odd and Even Field Filtering (see
Functional Description section for a full
discussion). Data is latched on the
rising edge of CLK.
CF
11-0
— Coefficient Input
CF
11-0
is used to load data into the
coefficient banks and configuration/
control registers. Data present on
CF
11-0
is latched into the LF Interface
TM
on the rising edge of CLK when LD is
LOW (see the LF Interface
TM
section for
a full discussion).
CA
7-0
— Coefficient Address
CA
7-0
determines which row of data in
the coefficient banks is fed to the
multipliers. CA
7-0
is latched into the
Coefficient Address Register on the
rising edge of CLK when CEN is LOW.
Outputs
DOUT
15-0
— Data Output
DOUT
15-0
is the 16-bit registered data
output port.
COUT
11-0
— Cascade Data Output
COUT
11-0
is a 12-bit cascade
output port. COUT
11-0
on one
device should be connected to
DIN
11-0
of another LF3330.
Controls
LD — Coefficient Load
When LD is LOW, data on CF
11-0
is latched into the LF Interface
TM
on the rising edge of CLK. When
LD is HIGH, data can not be
latched into the LF Interface
TM
.
When enabling the LF Interface
TM
for data input, a HIGH to LOW
transition of LD is required in
order for the input circuitry to
function properly. Therefore, LD
must be set HIGH immediately
after power up to ensure proper
operation of the input circuitry
(see the LF Interface
TM
section for
a full discussion).
PAUSE — LF Interface
TM
Pause
When PAUSE is HIGH, the LF
Interface
TM
loading sequence is halted
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control
registers at a slower rate than the
master clock (see the LF Interface
TM
section for a full discussion).
CEN
— Coefficient Address Enable
When CEN is LOW, data on CA
7-0
is
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA
7-0
is
not latched and the register’s contents
will not be changed.
F
IGURE
2.
I
NPUT
F
ORMATS
11 10 9
–2
11
(Sign)
2
2
2
1
2
1
0
2
0
2
10
2
9
11 10 9
–2
0
(Sign)
2
1
0
2
–1
2
–2
2
–9
2
–10
2
–11
Input Data
Coefficient Data
F
IGURE
3. A
CCUMULATOR
F
ORMAT
31 30 29
–2
20
(Sign)
2
1
0
2
19
2
18
2
–9
2
–10
2
–11
Accumulator Output
T
ABLE
1.
O
UTPUT
F
ORMATS
SLCT
4-0
S
15
S
14
S
13
· · ·
· · ·
· · ·
· · ·
S
8
S
7
· · ·
· · ·
· · ·
· · ·
S
2
S
1
S
0
00000
F
15
F
14
F
13
F
8
F
7
F
2
F
1
F
0
00001
F
16
F
15
F
14
F
9
F
8
F
3
F
2
F
1
00010
·
·
·
F
17
·
·
·
F
16
·
·
·
F
15
·
·
·
F
10
·
·
·
F
9
·
·
·
F
4
·
·
·
F
3
·
·
·
F
2
·
·
·
01110
F
29
F
28
F
27
· · ·
· · ·
· · ·
F
22
F
21
· · ·
· · ·
· · ·
F
16
F
15
F
14
01111
F
30
F
29
F
28
F
23
F
22
F
17
F
16
F
15
10000
F
31
F
30
F
29
F
24
F
23
F
18
F
17
F
16
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| LF3330QC15 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Vertical Digital Image Filter |
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