参数资料
型号: LF3330QC12
厂商: LOGIC DEVICES INC
元件分类: 数字信号处理外设
英文描述: Vertical Digital Image Filter
中文描述: 12-BIT, DSP-DIGITAL FILTER, PQFP100
封装: PLASTIC, QFP-100
文件页数: 5/15页
文件大小: 138K
代理商: LF3330QC12
DEVICES INCORPORATED
Video Imaging Products
5
LF3330
Vertical Digital Image Filter
11/08/2001–LDS.3330-M
F
IGURE
5.
M
ULTIPLE
LF3330
S
C
ASCADED
T
OGETHER
DIN
LINE BUFFERS
VERTICAL FILTER
RSL
CIRCUIT
COUT
DIN
RSL
CIRCUIT
COUT
COUT
RSL
CIRCUIT
LF3330
DIN
DIN
DATA OUT
29 TAP RESULT
LF3330
LF3330
LF3330
12
RSL
CIRCUIT
LINE BUFFERS
LINE BUFFERS
LINE BUFFERS
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
LF3347
RSL
CIRCUIT
16
25
25
FUNCTIONAL DESCRIPTION
Line Buffers
The maximum delay length of each line
buffer is 3076 cycles and the minimum
is 4 cycles. Configuration Register 0
(CR
0
) determines the delay length of
the line buffers. The line buffer length
is equal to the value of CR
0
plus 4. A
value of 0 for CR
0
sets the line buffer
length to 4. A value of 3072 for CR
0
sets the line buffer length to 3076. Any
values for CR
0
greater than 3072 are not
valid.
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register 1
determines which mode the line buffers
are in. In delay mode, the data input to
the line buffer is delayed by an amount
determined by CR
0
. In recirculate
mode, the output of the line buffer is
routed back to the input of the line
buffer allowing the line buffer contents
to be read multiple times.
Bit 1 of Configuration Register 1 allows
the line buffers to be loaded in parallel.
When Bit 1 is “1”, the input register
(DIN
11-0
) loads all seven line buffers in
parallel. This allows all the line buffers
to be preloaded with data in the
amount of time it normally takes to
load a single line buffer.
Odd and Even Field Filtering
The LF3330 is capable of odd and even
field filtering. Bit 2 of Configuration
Register 1 enables the VB Data Input
port required for odd and even field
filtering. Bit 3 of the same configura-
tion register enables the line buffer in
the VB Data path. Line buffer length is
set to the length written to Configura-
tion Register 0. If line buffer parallel
load is enabled and odd and even field
filtering is enabled, the data for the VB
line buffer comes from the VB Data
Input port.
Interleaved Data
The LF3330 is capable of handling
interleaved data. The number of data
sets it can handle is determined by the
number of data values contained in a
video line. If the interleaved video line
has 3076 data values or less, the LF3330
can handle it no matter how many data
sets are interleaved together.
Cascading
A cascade port is provided to allow
cascading of multiple devices for
more filter taps (see Figure 5).
COUT
11-0
of one device should be
connected to DIN
11-0
of another
device. As many LF3330s as desired
may be cascaded together. How-
ever, the outputs of the LF3330s
must be added together with exter-
nal adders.
The first line buffer on a cascaded
device must have its length short-
ened by two delays. This is to
account for the added delays of the
input register on the device and the
cascade output register from the
previous LF3330. If Bit 0 of Con-
figuration Register 3 is set to “1”,
the length of the first line buffer will
be reduced by two. This will make
its effective length the same as the
other line buffers on the device. If
Bit 0 of Configuration Register 3 is
set to “0”, the length of the first line
buffer will be the same as the other
line buffers. When cascading
devices, the first LF3330 should
have Bit 0 of Configuration Register
相关PDF资料
PDF描述
LF3330QC15 Vertical Digital Image Filter
LF43168 Dual 8-Tap FIR Filter
LF43168JC15 Digital Filter
LF43168JC22 Digital Filter
LF43168JC30 Digital Filter
相关代理商/技术参数
参数描述
LF3330QC15 制造商:LOGIC 制造商全称:LOGIC 功能描述:Vertical Digital Image Filter
LF3330QC18 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter
LF3330QC25 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter
LF3338 制造商:LOGIC 制造商全称:LOGIC 功能描述:8-Bit Vertical Digital Image Filter
LF3338QC12 制造商:LOGIC 制造商全称:LOGIC 功能描述:8-Bit Vertical Digital Image Filter