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参数资料
| 型号： | LF3330QC15 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 10/15页 |
| 文件大小： | 138K |
| 代理商： | LF3330QC15 |
DEVICES INCORPORATED
LF3330
Vertical Digital Image Filter
10
Video Imaging Products
11/08/2001–LDS.3330-M
T
ABLE
14.
L
IMIT
R
EGISTER
L
OADING
F
ORMAT
CF
11
CF
10
1st Word - Address
1
CF
9
1
CF
8
0
CF
7
0
CF
6
0
CF
5
0
CF
4
0
CF
3
0
CF
2
1
CF
1
1
CF
0
1
1
2nd Word- Data
R
R
R
R
0
1
1
0
0
0
0
0
3rd Word - Data
R
R
R
R
0*
0
1
1
1
0
1
1
4th Word - Data
R
R
R
R
1
0
1
0
0
1
0
0
5th Word - Data
R
R
R
R
0**
1
1
1
0
0
1
0
R = Reserved. Must be set to “0”.
* This bit represents the MSB of the Lower Limit.
** This bit represents the MSB of the Upper Limit.
T
ABLE
13.
S
ELECT
R
EGISTER
L
OADING
F
ORMAT
CF
11
CF
10
1st Word - Address
0
CF
9
1
CF
8
0
CF
7
0
CF
6
0
CF
5
0
CF
4
0
CF
3
0
CF
2
0
CF
1
1
CF
0
0
1
2nd Word - Data
0
0
0
0
0
0
0
0
1
1
1
1
configuration register. Data value
003H is written into Configuration
Register 2. Table 12 shows an
example of loading data into a
round register. Data value
7683F4A2H is written into round
register 12. Table 13 shows an
example of loading data into a select
register. Data value 00FH is loaded
into select register 2. Table 14
shows an example of loading data
into limit register 7. Data value
3B60H is loaded as the lower limit
and 72A4H is loaded as the upper
limit.
It takes 9S clock cycles to load S
coefficient sets into the device. There-
fore, it takes 2304 clock cycles to load
all 256 coefficient sets. Assuming an
83 MHz clock rate, all 256 coefficient
sets can be updated in less than 27.7 μs,
which is well within vertical blanking
time. It takes 5S clock cycles to load S
round or limit registers. Therefore, it
takes 160 clock cycles to update all
round and limit registers. Assuming an
83 MHz clock rate, all round/ limit
registers can be updated in 1.92 μs.
The coefficient banks and configura-
tion/ control registers are not loaded
with data until all data values for
the specified address are loaded into
the LF Interface
TM
. In other words,
the coefficient banks are not written
to until all eight coefficients have
been loaded into the LF Interface
TM
.
A round register is not written to
until all four data values are loaded.
After the last data value is loaded,
the interface will expect a new
address value on the next clock
cycle. After the next address value
is loaded, data loading will begin
again as previously discussed. As
long as data is loaded into the
interface, LD must remain LOW.
After all desired coefficient banks
and configuration/ control registers
are loaded with data, the LF
Interface
TM
must be disabled. This is
done by setting LD HIGH on the clock
cycle after the clock cycle which
latches the last data value. It is
important that the LF Interface
TM
remain disabled when not loading
data into it.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LF3330QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3330QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3338 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:8-Bit Vertical Digital Image Filter |
| LF3338QC12 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:8-Bit Vertical Digital Image Filter |
| LF3347 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:High-Speed Image Filter with Coefficient RAM |
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