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参数资料
| 型号： | LF3330QC15 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 9/15页 |
| 文件大小： | 138K |
| 代理商： | LF3330QC15 |
DEVICES INCORPORATED
Video Imaging Products
9
LF3330
Vertical Digital Image Filter
11/08/2001–LDS.3330-M
REGISTER
ADDRESS (HEX)
0
1
A00
A01
14
15
A0E
A0F
T
ABLE
7. R
OUND
R
EGISTERS
REGISTER
ADDRESS (HEX)
0
1
E00
E01
14
15
E0E
E0F
T
ABLE
9. L
IMIT
R
EGISTERS
REGISTER
ADDRESS (HEX)
0
1
600
601
14
15
60E
60F
T
ABLE
8. S
ELECT
R
EGISTERS
11 10 9
DESCRIPTION
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
Coefficient Banks
Configuration Registers
Select Registers
Round Registers
Limit Registers
T
ABLE
6. CF
11-9
D
ECODE
T
ABLE
11.
C
ONFIGURATION
R
EGISTER
L
OADING
F
ORMAT
CF
11
CF
10
1st Word - Address
0
CF
9
1
CF
8
0
CF
7
0
CF
6
0
CF
5
0
CF
4
0
CF
3
0
CF
2
0
CF
1
1
CF
0
0
0
2nd Word - Data
0
0
0
0
0
0
0
0
0
0
1
1
significant bits (CF
11-9
) determine if
the LF Interface
TM
will load coefficient
banks or configuration/ control
registers (see Table 6). The nine least
significant bits (CF
8-0
) are the address
for whatever is to be loaded (see
Tables 7 through 9). For example, to
load address 15 of the coefficient
banks, the first data value into the
LF Interface
TM
should be 00FH. To
load limit register 10, the first data
value should be E0AH. The first
address value should be loaded into
the interface on the same clock cycle
that latches the HIGH to LOW
transition of LD (see Figures 6 and 7).
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the interface
will expect eight values to be loaded
into the device after the address value.
The eight values are coefficients 0
through 7. When loading configura-
tion or select registers, the interface
will expect one value after the address
value. When loading round or limit
registers, the interface will expect four
values after the address value. Fig-
ures 6 and 7 show the data loading
sequences for the coefficient banks
and configuration/ control registers.
PAUSE allows the user to effectively
slow the rate of data loading through
the LF Interface
TM
. When PAUSE is
HIGH, the LF Interface
TM
is held until
PAUSE is returned to a LOW. Figures
8 through 11 display the effects of
PAUSE while leading coefficient and
control data.
Table 10 shows an example of
loading data into the coefficient
banks. The following data values
are written into address 10 of
coefficient banks 0 through 7: 210H,
543H, C76H, 9E3H, 701H, 832H,
F20H, 143H. Table 11 shows an
example of loading data into a
T
ABLE
12.
R
OUND
R
EGISTER
L
OADING
F
ORMAT
CF
11
CF
10
1st Word - Address
1
CF
9
1
CF
8
0
CF
7
0
CF
6
0
CF
5
0
CF
4
0
CF
3
1
CF
2
1
CF
1
0
CF
0
0
0
2nd Word- Data
R
R
R
R
1
0
1
0
0
0
1
0*
3rd Word - Data
R
R
R
R
1
1
1
1
0
1
0
0
4th Word - Data
R
R
R
R
1
0
0
0
0
0
1
1
5th Word - Data
R
R
R
R
0**
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
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