参数资料
型号: LFEC20E-3FN484I
厂商: Lattice Semiconductor Corporation
文件页数: 111/163页
文件大小: 0K
描述: IC FPGA 19.7KLUTS 484FPBGA
标准包装: 60
系列: EC
逻辑元件/单元数: 19700
RAM 位总计: 434176
输入/输出数: 360
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BBGA
供应商设备封装: 484-FPBGA(23x23)
3-15
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-5. DDR Timings
tDQVBS
Data Valid Before DQS
All
0.20
0.20
0.20
UI
tDQVAS
Data Valid After DQS
All
0.20
0.20
0.20
UI
fMAX_DDR
DDR Clock Frequency
All
95
200
95
166
95
133
MHz
Primary and Secondary Clock6
fMAX_PRI
2
Frequency for Primary Clock Tree
All
420
378
340
MHz
tW_PRI
Clock Pulse Width for Primary
Clock
All
1.19
1.19
1.19
ns
tSKEW_PRI
Primary Clock Skew within an I/O
Bank
All
250
300
350
ps
1. General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF.
2. Using LVDS I/O standard.
3. DDR timing numbers based on SSTL I/O.
4. DDR specifications are characterized but not tested.
5. UI is average bit period.
6. Based on a single primary clock.
7. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool
uses internal parameters that have been characterized but are not tested on every device.
Timing v.G 0.30
LatticeECP/EC External Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Device
-5
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
tDQVAS
tDQVBS
DQ and DQS Write Timings
t
DQS
DQ
DQS
DQ
DVEDQ
tDVADQ
DQ and DQS Read Timings
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