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参数资料
型号： LFEC20E-3FN484I
厂商： Lattice Semiconductor Corporation
文件页数： 72/163页
文件大小： 0K
描述： IC FPGA 19.7KLUTS 484FPBGA
标准包装： 60
系列： EC
逻辑元件/单元数： 19700
RAM 位总计： 434176
输入/输出数： 360
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： -40°C ~ 100°C
封装/外壳： 484-BBGA
供应商设备封装： 484-FPBGA（23x23）
7-3
Revision History
LatticeECP/EC Family Data Sheet
September 2005
02.0
Architecture
sysIO section has been updated.
DC & Switching
Characteristics
Recommended Operating Conditions has been updated with VCCPLL.
DC Electrical Characteristics table has been updated
Removed 5V Tolerant Input Buffer section.
Register-to-Register performance table has been updated (rev. G 0.28).
LatticeECP/EC External Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Internal Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28).
sysCLOCK PLL timing table has been updated (rev. G 0.28)
LatticeECP/EC sysCONFIG Port Timing specification table has been
updated (rev. G 0.28).
Master Clock table has been updated (rev. G 0.28).
JTAG Port Timing specification table has been updated (rev. G 0.28).
Pinout Information
Signal Description table has been updated with VCCPLL.
November 2005
02.1
DC & Switching
Characteristics
Pin-to-Pin Performance table has been updated (G 0.30)
- 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX
Register-to-Register Performance (G 0.30) - No timing number
changes.
External Switching Characteristics (G 0.30) - No timing number
changes.
Internal Switching Characteristics (G 0.30)
-tSUP_DSP, tHP_DSP, tSUO_DSP, tHO_DSP, tCOI_DSP, tCOD_DSP numbers
have been updated.
Family Timing Adders (G 0.30) - No timing number changes.
sysCLOCK PLL Timing (G 0.30) - No timing number changes.
sysCONFIG Port Timing Specifications (G 0.30) - No timing number
changes.
Master Clock (G 0.30) - No timing number changes.
JTAG Port Timing Specification (G 0.30) - No timing number changes.
Ordering Information
Added 208-PQFP lead-free part numbers.
March 2006
02.2
DC & Switching
Characteristics
Added footnote 3. to VCCAUX in the Recommended Operating Condi-
tions table.
January 2007
02.3
Architecture
EBR Asynchronous Reset section added.
February 2007
02.4
Architecture
Updated EBR Asynchronous Reset section.
Updated Maximum Number of Elements in a Block table - MAC value for
x9 changed to 2.
May 2007
02.5
Architecture
Updated text in Ripple Mode section.
November 2007
02.6
DC & Switching
Characteristics
Added JTAG Port Waveforms diagram.
Updated tRST timing information in the sysCLOCK PLL Timing table.
Pinout Information
Added Thermal Management text section.
Supplemental
Information
Updated title list.
February 2008
02.7
DC & Switching
Characteristics
Read/Write Mode (Normal) and Read/Write Mode with Input and Output
Registers waveforms in the EBR Memory Timing Diagrams section
have been updated.
September 2012
02.8
All
Updated document with new corporate logo.
Date
Version
Section
Change Summary
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相关代理商/技术参数
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LFEC20E-3FN672C 功能描述:FPGA - 现场可编程门阵列 19.7K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
LFEC20E-3FN672I 功能描述:FPGA - 现场可编程门阵列 19.7K LUTs 400 IO 1. 2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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LFEC20E-3Q208I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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