July 2007
Data Sheet DS1001
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1001 Introduction_01.5
Features
Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
No external configuration memory
Excellent design security, no bit stream to
intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through system configuration and JTAG ports
Sleep Mode
Allows up to 1000x static current reduction
TransFR Reconfiguration (TFR)
In-field logic update while system operates
Extensive Density and Package Options
3.1K to 19.7K LUT4s
62 to 340 I/Os
Density migration supported
Embedded and Distributed Memory
54 Kbits to 396 Kbits sysMEM Embedded
Block RAM
Up to 79 Kbits distributed RAM
Flexible memory resources:
Distributed and block memory
Flexible I/O Buffer
Programmable sysIO buffer supports wide
range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
– SSTL 18 Class I
SSTL 3/2 Class I, II
– HSTL15 Class I, III
HSTL 18 Class I, II, III
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
Dedicated DDR Memory Support
Implements interface up to DDR333 (166MHz)
sysCLOCK PLLs
Up to 4 analog PLLs per device
Clock multiply, divide and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY internal logic analyzer capability
Onboard oscillator for configuration
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
Table 1-1. LatticeXP Family Selection Guide
Device
LFXP3
LFXP6
LFXP10
LFXP15
LFXP20
PFU/PFF Rows
16
24
32
40
44
PFU/PFF Columns
2430384856
PFU/PFF (Total)
384
720
1216
1932
2464
LUTs (K)
3
6
101520
Distributed RAM (KBits)
1223396179
EBR SRAM (KBits)
54
72
216
324
396
EBR SRAM Blocks
6
8
24
36
44
VCC Voltage
1.2/1.8/2.5/3.3V
PLLs
22444
Max. I/O
136
188
244
300
340
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
62
144-pin TQFP (20 x 20 mm)
100
208-pin PQFP (28 x 28 mm)
136
142
256-ball fpBGA (17 x 17 mm)
188
388-ball fpBGA (23 x 23 mm)
244
268
484-ball fpBGA (23 x 23 mm)
300
340
LatticeXP Family Data Sheet
Introduction