参数资料
型号: LIS302DLH
厂商: STMICROELECTRONICS
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PBGA14
封装: 3 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, LGA-14
文件页数: 13/37页
文件大小: 673K
代理商: LIS302DLH
Digital interfaces
LIS302DLH
20/37
Doc ID 15797 Rev 1
Figure 6.
Read and write protocol
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiple of 8 in case of multiple bytes read/write. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address is auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When MS
bit is ‘0’ the address used to read/write data remains the same for every block. When MS bit
is ‘1’ the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
5.2.1
SPI read
Figure 7.
SPI read protocol
CS
SPC
SDI
SDO
RW
AD5 AD4 AD3 AD2 AD1 AD0
DI7DI6 DI5DI4 DI3DI2 DI1DI0
DO7DO6 DO5DO4 DO3DO2 DO1DO0
MS
CS
SPC
SDI
SDO
RW
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
AD5 AD4 AD3 AD2 AD1 AD0
MS
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